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| preliminary this document contains in f o r mation on a product under d e v elopment at ad v anced micro d e vice s . the in f o r mation is intended to help y ou e v aluate this product . amd rese r v es the r ight to change or discontinue wo r k on this proposed product without notic e . pu b lication# 20183 r e v : b amendment/ 0 issue date : april 1997 1 AM79C930 pcnet -mobile single-chi p wireless lan media access cont r oller distinctive char a cteristics n capable of suppo r ting the ieee 802.11 standa r d (draft) n suppo r ts the xi r com netw a ve media access cont r ol (m a c) p r otocols n suppo r ts m a c l a yer functions n individual 8- b yte transmit and 15- b yte receive fifos n integrated intelligent 80188 p r ocessor f or m a c l a yer functions n glueless pcmcia b us interface con f orming to pc ca r d standa r d?eb . 1995 n full pcmcia software interface suppo r t f or pc ca r d standa r d?eb . 1995 n glueless isa (ieee p996) b us interface with full suppo r t f or plug and pl a y release 1.0a n glueless sram interface f or m a c operations , suppo r ting up to 128 k b ytes of memory n glueless flash memory interface , suppo r ting up to 128 k b ytes of non- v olatile memory f or m a c cont r ol code , pcmcia con?uration paramete r s , and isa plug and pl a y con?uration paramete r s n p ro vides integrate d t ransceiver attachment interface ( t ai) , suppo r ting frequency-hopping spread spectrum , direct sequence spread spectrum , and infrared p h ysical-l a yer interfaces n antenna dive r sity selection suppo r t n f abricated with submic r on cmos technology with l o w operating current n suppo r ts dual 3 v and 5 v supp l y applications n l o w-p o wer mode all o ws reduced p o wer consumption f or critical battery-p o wered applications n 144-pi n thin quad flat p a c k (tqfp) pa c kage a v ailable f or space-critical applications , such as pcmcia n j t a g boundary scan (ieee 1149.1) test access po r t f or boa r d-l e vel p r oduction test general description pcnet-mobile (AM79C930) is the ?st in a se r ies of mo- bile net w o r king products in amd s pcnet f amil y . the AM79C930 d e vice is the ?st single-chip wireless lan media access controller (m a c) suppo r ting the ieee 802.11 (d r aft) standard and the xircom net w a v e m a c protocol s . the AM79C930 d e vice is designed to h a v e a e xi b le protocol engine to all o w f or indust r y standard and prop r ieta r y protocol s . protocol r m w are f or xircom net w a v e and ieee 802.11 (draft) m a c pro- tocols are supplied b y am d . it is pin-compati b le with the pcmcia b us or the isa (plug and pl a y) b u s through a pin-strapping option. the AM79C930 d e vice contains a pcmcia/isa b u s inter f ace unit (biu), a m a c control unit, and a t r anscei v er attachment inter f ace ( t ai) . th e t ai sup- ports frequency-hopping spread spect r um, direct sequence spread spect r um, and infrared p h ysical l a y e r inter f ace s . in addition, a p o wer d o wn function has been inco r porated to pr o vide l o w stand b y current f or p o wer- sensiti v e application s . the AM79C930 d e vice pr o vides users with a media ac- cess controller that has e xibility (i. e ., b us inter f ac e , protocol, and p h ysical l a y er suppo r t) to all o w the design of m ultiple products using a single d e vic e . by h a ving all the necessa r y m a c functions on a single chi p , users only need to add memo r y and the p h ysical l a y er in order to deli v er a fully functional wireless lan connection.
2 AM79C930 preliminary ordering inform a tion standa r d p r oducts amd standard products are a v aila b le in s e v e r al pa c kages and operating r ange s . the order number ( v alid combination) is f o r med b y a combination of the elements bel o w . v alid combinations v alid combinations list con gurations planned to be sup- po r ted in v olume f or this d e vic e . consult the local amd sales of ce to con r m a v ailability of speci c v alid combinations and to che c k on n e wly released combination s . AM79C930 v c device number/description AM79C930 single-chip wireless lan media access controller optional p r ocessing \w = trimmed and formed in a tray oper a ting conditions c = commercial ( 0 c to +7 0 c) p a ck a g e type v = 144- pin thin quad flat pack (pqt144) speed not applicable \w v alid combinations AM79C930 vc\w AM79C930 3 preliminary block di a gram pcmcia mode jtag control block trst tms/t3 tdi/t1 tdo/t2 rxcin antslt antslt sar6? adin2? adref rxdata sdclk sddata sdsel3? txcmd txcmd txmod txdata txdata rxpe txpe hfpe hfclk lfpe lfclk fdet lnk act rxc transceiver attachment interface mac control unit (80188 core) bus interface unit (pcmcia) moe mwe ma 16? md 7? xce sce fce user6? a14? d7? reg ce1 oe iord iowr reset we wait inpack ireq stschg pmx2? clkin test pwrdwn ca16? cad 7? int1 ale wr srdy ucs lcs reset drq0 drq1 int0 20183 b -1 4 AM79C930 preliminary block di a gram bus interface unit a14? or la23?7, sa16? d7? clkin slave control pcmci a and is a memory and i/o address bu f fer data bu f fer sir0 system interrupt generator sir1 ... sir7 is a memory base is a i/o base md[7:0] ma[16:0] 80188 interrupt generator ireq pcmci a config registers ale ca16 latch bus multi- plexer cad7? ca15? mir0 mir1 ... mir15 moe mwe ucs lcs srdy xce fce taice sce int1 reset pcmcia or is a control signals plug and play control module slave control and arbitration for memory interface bus 20183 b -2 AM79C930 5 preliminary block di a gram t ransceiver atta c hment interface unit c r c ma[4:0] md[7:0] clkin slave control memory interface bus i/o and dma tir0 interrupt generator tcr31 tx fifo 8 bytes txd reset tcr.. . tir... tir31 tcr0 irq drq[1:0] rx fifo 15 bytes p->s s->p c r c rxd sfd detect fde t ?0 ? ?0 ?0 m u x txc dpll m u x rxcin rxcsel rxc c t ransceiver control signals t ransceiver interface unit control count empty bias suppress mux phylen mux ?0 taice slave control sleep 20183 b -3 amd p r e l i m i n a r y 6 AM79C930 table of contents distinctive characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general description 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ordering information 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . block diagram 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcmcia mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bus interface unit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transceiver attachment interface unit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcmcia block diagram 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcmcia connection diagram 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcmcia pin summary 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . listed by pin number 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcmcia pin list 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . listed by pin name 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcmcia pin function summary 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcmcia pin summary 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isa plug and play block diagram 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . connection diagram 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isa plug and play 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isa plug and play pin list 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . listed by pin number 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . listed by pin name 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isa plug and play pin summary 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin descriptions 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pins with internal pull up or pull down devices 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . configuration pins 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . host system interface pins 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcmcia bus interface 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isa (ieee p996) bus interface 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . memory interface pins 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clock pins 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . system management pins 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tai interface pins 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . other pins 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ieee 1149.1 test access port pins 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power supply pins 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . analog power supply pins 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital power supply pins 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . multi-function pins 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 1: user2/la19 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 2: user3/sa16 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p r e l i m i n a r y amd 7 AM79C930 pin 3: user4/la17 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 45: stschg/bale 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 90: user0/rfrsh 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 91: user1/irq12/extcts/exint188 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 92: user7/irq11 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 94: rxc/irq10/exta2dst 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 95: user6/irq5/extsdf 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 96: user5/irq4/extchbsy 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 98: act 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 100: lnk 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 101: sdclk 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 102: sddata 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 103: sdsel3 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 105: sdsel2 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 107: sdsel1 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 115: txc 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 118: lfpe 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 120: hfpe 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 122: rxpe 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 126: txcmd 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 129: txpe 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 131: txmod 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 132: antslt 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 141: antslt/la23 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 142: txcmd/la21 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 143: txdata/la20 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin 144: llocke/sa15 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . functional description 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . basic functions 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . system bus interface function 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . memory bus interface function 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . software interface function 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . network interface function 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . detailed functions 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . block level description 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bus interface unit 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcmcia interface 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isa (ieee p996) plug and play interface 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . memory interface 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . embedded 80188 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . media access management 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . medium allocation 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . initialization 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sram memory management 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . flash memory management 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transceiver attachment interface unit management 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . amd p r e l i m i n a r y 8 AM79C930 bus interface unit interaction 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transceiver attachment interface unit 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tx fifo 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tx power ramp control 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AM79C930-based tx power ramp control . 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transceiver-based tx power ramp control . 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tx crc generation 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tx status 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . start of frame delimiter detection 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rx data parallelization 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rx fifo 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rx crc checking 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rx status reporting 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bit ordering 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rssi a/d unit 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . physical header accommodation 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc bias control 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . baud determination logic 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clear channel assessment logic 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . automatic antenna diversity logic 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . txc as input 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ieee 1149.1 test access port interface 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . boundary scan circuit 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tap fsm 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supported instructions 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . instruction register and decoding logic 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . boundary scan register (bsr) 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . other data registers 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power saving modes 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power down function 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . applicability to ieee 802.11 power down modes 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . software access 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AM79C930 system interface resources 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcmcia mode resources 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcmcia attribute memory resources. 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcmcia i/o resources. 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isa plug and play mode resources 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isa plug and play memory resources 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isa plug and play i/o resources. 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isa plug and play register set. 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mac firmware resources 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mac (80188 core) memory resources 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mac (80188 core) memory resources restrictions 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mac (80188 core) interrupt channel allocation 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mac (80188 core) dma channel allocation 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dma channel allocation in the 80188 core 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . loopback operation 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p r e l i m i n a r y amd 9 AM79C930 led support 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset methods 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset pin 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . swreset (sir0[7]) 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . coreset (sir0[6]) 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcmcia cor sreset 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isa pnp reset 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sres (tir0[5]) 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . register descriptions 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . system interface registers (sir space) 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sir0: general configuration register (gcr) 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sir1: bank switching select register (bss) 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sir2: local memory address register [7:0] (lma) 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sir3: local memory address register [14:8] (lma) 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sir4: i/o data port a (iodpa) 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sir5: i/o data port b (iodpb) 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sir6: i/o data port c (iodpc) 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sir7: i/o data port d (iodpd) 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mac interface registers (mir space) 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mir0: processor interface register (pir) 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mir1: power up clock time [3:0] (puct) 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mir2: power down length count [7:0] (pdlc) 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mir3: power down length count [15:8] (pdlc) 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mir4: power down length count [22:16] (pdlc) 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mir5: free count [7:0] (fcnt) 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mir6: free count [15:8] (fcnt) 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mir7: free count [23:16] (fcnt) 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mir8: flash wait states 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mir9: tcr mask stschg data 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mir10: reserved 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mir11: reserved 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mir12: reserved 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mir13: reserved 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mir14: reserved 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mir15: reserved 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transceiver attachment interface registers (tir space) 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir0: network control 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir1: network status 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir2: serial device 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir3: fast serial port control 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir4: interrupt register 1 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir5: interrupt register 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir6: interrupt unmask register 1 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir7: interrupt unmask register 2 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir8: transmit control 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir9: transmit status 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . amd p r e l i m i n a r y 10 AM79C930 tir10: tx fifo data register 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir11: transmit sequence control 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir12: byte count register lsb 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir13: byte count register msb 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir14: byte count limit lsb 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir15: byte count limit msb 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir16: receiver control 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir17: receive status register 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir18: rx fifo data register 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir19: reserved 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir20: crc32 correct byte count lsb 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir21: crc32 correct byte count msb 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir22: crc8 correct byte count lsb 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir23: crc8 correct byte count msb 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir24: tcr index register 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir25: configuration data port 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir26: antenna diversity and a/d control 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir27: serial approximation register 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir28: rssi lower limit 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir29: user pin data 103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir30: test dummy register 103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tir31: test 103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tai configuration register space (tcr) 103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr0: network configuration 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr1: transmit configuration 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr2: clock recovery 105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr3: receive configuration 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr4: antenna diversity timer 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr5: tx ramp up timing 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr6: tx ramp down timing 108 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr7: pin data a 108 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr8: start delimiter lsb 109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr9: start delimiter csb 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr10: start delimiter msb 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr11: interrupt register 3 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr12: interrupt unmask register 3 111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr13: pin configuration a 111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr14: pin configuration b 112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr15: pin configuration c 113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr16: baud detect start 114 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr17: baud detect lower limit 115 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr18: baud detect upper limit. 115 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr19: baud detect accept count for carrier sense 116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr20: baud detect accept count for stop diversity 116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr21: baud detect ratio 116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr22: baud detect accept count 117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr23: baud detect fail count 117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p r e l i m i n a r y amd 11 AM79C930 tcr24: rssi sample start 117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr25: rssi configuration 118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr26: reserved 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr27: tip led scramble 120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr28: clear channel assessment configuration 121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr29: reserved 122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr30: pin function and data rate 122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tcr31: device revision 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcmcia ccr registers and pcmcia cis space 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcmcia card configuration and status register 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcmcia card information structure (cis) 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating ranges 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc characteristics 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 v AM79C930 dc characteristics 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 v AM79C930 dc characteristics 128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ieee 1149.1 dc characteristics (5.0 and 3.3 v) 130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings 131 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating ranges 131 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ac characteristics 131 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 and 3.3 v pcmcia interface ac characteristics 131 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcmcia memory read access 131 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcmcia memory write access 132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcmcia i/o read access 133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcmcia i/o write access 134 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 and 3.3 v isa interface ac characteristics 135 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isa access 136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 v memory bus interface ac characteristics 137 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . memory bus read access 137 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . memory bus write access 138 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 v memory bus interface ac characteristics 139 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . memory bus read access 139 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . memory bus write access 140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 v tai interface ac characteristics 141 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 v tai interface ac characteristics 144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 and 3.3 v user programmable pins ac characteristics 146 . . . . . . . . . . . . . . . . . . . . . . . . 5.0 and 3.3 v ieee 1149.1 interface ac characteristics 147 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . analog-to-digital (a/d) converter characteristics 147 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . amd p r e l i m i n a r y 12 AM79C930 timing waveforms 148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pcmcia bus interface waveforms 148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . isa bus interface waveforms 150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . memory bus interface waveforms 151 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clock waveforms 152 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tai waveforms 153 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . programmable interface waveforms 154 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ieee 1149.1 interface waveforms 155 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ac test reference waveforms 156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 v pcmcia ac test reference waveform 156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 v pcmcia ac test reference waveform 156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 v non-pcmcia ac test reference waveform 157 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 v non-pcmcia ac test reference waveform 157 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . physical dimensions 158 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . appendix a: typical AM79C930 system application a-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device configuration a-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . frame transmission a-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . frame reception a-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AM79C930 13 preliminary pcmcia connection di a gram notes: pin 1 is marked for orientation. nc = no connection 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 56 57 58 59 60 61 62 98 99 100 101 102 103 104 54 55 53 108 107 106 105 31 4 5 6 7 8 9 10 1 1 1 2 3 28 29 30 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 32 33 34 35 36 user2 user3 user4 vddm xce ma11 vssm ma9 ma8 ma13 mwe ma14 ma16 ma15 ma12 vddm v cc ma7 ma6 ma5 vssm ma4 ma3 ma2 ma1 ma0 md0 md1 vddm md2 md3 vssm md4 md5 md6 md7 llocke txdata txcmd antslt vddu2 vdd5 avdd adref avss adin2 adin1 pwrdwn antslt txmod vsst txpe fdet v ss txcmd vddt rxcin rxsdata rxpe txdata hfpe hfclk lfpe lfclk vsst txc sar6 sar5 sar4 sar3 sar2 sar1 sar0 sdsel1 vsst sdsel2 vddt sdsel3 addata sdclk lnk vsst act vddu1 user5 user6 rxc vssu1 user7 user1 user0 v cc tdi trst tms tdo tck pmx1 pmx2 test clk20 pcmcia d3 d4 vssp d5 d6 d7 ma10 moe sce fce d2 d1 d0 vssp stschg a0 a1 reg a2 inpack a3 wait a4 a7 vddp a12 v ss reset a5 a6 ireq we a14 a13 a8 iowr iord a9 a11 oe a10 ce1 132 131 130 129 128 127 126 125 124 123 122 144 143 142 141 140 139 138 137 136 135 134 133 121 120 1 19 1 18 1 17 1 16 1 15 1 14 1 13 1 12 1 1 1 1 10 109 42 43 44 45 46 47 48 49 50 51 52 40 41 37 38 39 AM79C930 20183 b -4 1 4 AM79C930 preliminary pcmcia pin summa r y listed b y pin number pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 user2 37 ma10 73 d7 109 sar1 2 user3 38 moe 74 d6 110 sar2 3 user4 39 sce 75 d5 111 sar3 4 vddm 40 fce 76 vssp 112 sar4 5 xce 41 d2 77 d4 113 sar5 6 ma11 42 d1 78 d3 114 sar6 7 vssm 43 d0 79 pcmcia 115 txc 8 ma9 44 vssp 80 clk20 116 vsst 9 ma8 45 stschg 81 test 117 lfclk 10 ma13 46 a0 82 pmx2 118 lfpe 11 mwe 47 a1 83 pmx1 119 hfclk 12 ma14 48 reg 84 tck 120 hfpe 13 ma16 49 a2 85 tdo 121 tx d a t a 14 ma15 50 inp a ck 86 tms 122 rxpe 15 ma12 51 a3 87 trst 123 rx d a t a 16 vddm 52 w ait 88 tdi 124 rxcin 17 v cc 53 a4 89 v cc 125 vddt 18 ma7 54 a7 90 user0 126 txcmd 19 ma6 55 vddp 91 user1 127 v ss 20 ma5 56 a12 92 user7 128 fdet 21 vssm 57 v ss 93 vssu1 129 txpe 22 ma4 58 reset 94 rxc 130 vsst 23 ma3 59 a5 95 user6 131 txmod 24 ma2 60 a6 96 user5 132 ants l t 25 ma1 61 ireq 97 vddu1 133 pwr d wn 26 ma0 62 we 98 a ct 134 adin1 27 md0 63 a14 99 vsst 135 adin2 28 md1 64 a13 100 lnk 136 a vss 29 vddm 65 a8 101 sdclk 137 adref 30 md2 66 io wr 102 sd d a t a 138 a vdd 31 md3 67 iord 103 sdsel3 139 vdd5 32 vssm 68 a9 104 vddt 140 vddu2 33 md4 69 a11 105 sdsel2 141 antsl t 34 md5 70 oe 106 vsst 142 txcmd 35 md6 71 a10 107 sdsel1 143 txd a t a 36 md7 72 ce1 108 sar0 144 llocke AM79C930 15 preliminary pcmcia pin list listed b y pin name pin name pin no. pin name pin no. pin name pin no. pin name pin no. a0 46 hfpe 120 oe 70 txmod 131 a1 47 inp a ck 50 pcmcia 79 txpe 129 a10 71 iord 67 pmx1 83 user0 90 a11 69 io wr 66 pmx2 82 user1 91 a12 56 ireq 61 pwr d wn 133 user2 1 a13 64 lfclk 117 reg 48 user3 2 a14 63 lfpe 118 reset 58 user4 3 a2 49 llocke 144 rxc 94 user5 96 a3 51 lnk 100 rxcin 124 user6 95 a4 53 ma0 26 rx d a t a 123 v cc 17 a5 59 ma1 25 rxpe 122 v cc 89 a6 60 ma10 37 sar0 108 vdd5 139 a7 54 ma11 6 sar1 109 vddm 4 a8 65 ma12 15 sar2 110 vddm 16 a9 68 ma13 10 sar3 111 vddm 29 a ct 98 ma14 12 sar4 112 vddp 55 adin1 134 ma15 14 sar5 113 vddt 104 adin2 135 ma16 13 sar6 114 vddt 125 adref 137 ma2 24 sce 39 vddu1 97 ants l t 132 ma3 23 sdclk 101 vddu2 140 antsl t 141 ma4 22 sd d a t a 102 v ss 57 a vdd 138 ma5 20 sdsel1 107 v ss 127 a vss 136 ma6 19 sdsel2 105 vssm 7 ce1 72 ma7 18 sdsel3 103 vssm 21 clk20 80 ma8 9 stschg 45 vssm 32 d0 43 ma9 8 tck 84 vssp 44 d1 42 md0 27 tdi 88 vssp 76 d2 41 md1 28 tdo 85 vsst 99 d3 78 md2 30 test 81 vsst 106 d4 77 md3 31 tms 86 vsst 116 d5 75 md4 33 trst 87 vsst 130 d6 74 md5 34 txc 115 vssu1 93 d7 73 md6 35 txcmd 126 w ait 52 fce 40 md7 36 txcmd 142 user7 92 fdet 128 moe 38 tx d a t a 121 we 62 hfclk 119 mwe 11 txd a t a 143 xce 5 1 6 AM79C930 preliminary pcmcia pin function summa r y pcmcia pin summary no . of pins pin name pin function pin style 15 a14?0 pcmcia address b us lines i 8 d7?0 pcmcia data b us lines ts2 1 reset pcmcia b us reset line i 1 ce1 card ena b le 1?sed to ena b le the d7? pins f or pcmcia read an d w r ite accesses i 1 oe output ena b le?sed to ena b le the output d r i v ers of the AM79C930 d e vice f or pcmcia read accesses i 1 we w r ite ena b le?sed to indicate that the current pcmcia cycle is a w r ite access i 1 reg reg?sed to indicate that the current pcmcia cycle is to the att r i b ute memo r y space of the AM79C930 d e vice i 1 inp a ck input a c kn o wledge?sed to indicate that the AM79C930 d e vice will respond to the current i/o read cycle ts1 1 w ait w ait?sed to del a y the te r mination of the current pcmcia cycle ts2 1 iord i/o read?his signal is asse r ted b y the pcmcia host system when e v er an i/o read operation occurs 1 io wr i/ o w r ite?his signal is asse r ted b y the pcmcia host system when e v er an i/o w r ite ope r ation occurs i 1 ireq inter r upt request?his line is asse r ted when the AM79C930 d e vice needs se r vicing from the soft w are pts3 1 stschg status change?cmcia output used only f o r w akeup signaling pts1 1 pcmcia pcmcia mode?elects pcmcia or isa plug and pl a y mode i 1 pwr d wn p o werd o wn?ndicates that d e vice is in the p o wer d o wn mode tp1 17 ma16? memo r y address bus?hese lines are used to address locations in the flash d e vic e , the sram d e vic e , and an e xtra pe r iphe r al d e vice that are contained within an AM79C930-based design tp1 8 md7? memo r y data bus?hese lines are used to w r ite and read data to/from flash, sram, and/or an e xtra pe r iphe r al d e vice within an AM79C930-based design ts1 1 fce flash chip ena b le?his signal becomes asse r ted when the flash d e vice has been addressed b y either the 80188 core of the AM79C930 d e vice or b y the soft w are through the pcmcia inter f ace tp1 1 sce sram chip ena b le?his signal becomes asse r ted when the sram d e vice has been addressed b y either the 80188 core of the AM79C930 d e vice or b y the soft w are through the pcmcia inter f ace tp1 1 xce extra chip ena b le?his signal becomes asse r ted when the e xtra pe r iphe r al d e vice has been addressed b y the 80188 core of the AM79C930 d e vice (xce is not accessi b le through the system inter f ace) tp1 1 moe memo r y output ena b le?his signal becomes asse r ted du r ing reads of d e vices located on the memo r y inter f ace b us tp1 1 mwe memo r y w r ite ena b le?his signal becomes asse r ted du r ing w r ites to d e vices located on the memo r y inter f ace b us tp1 1 tck t est clo c k?his is the clo c k signal f or ieee 1149.1 testing i 1 tdi t est data in?his is the data input signal f or ieee 1149.1 testing i AM79C930 1 7 preliminary pcmcia pin function summa r y (continued) pcmcia pin summary (conti n ued) no . of pins pin name pin function pin style 1 tdo t est data out?his is the data output signal f or ieee 1149.1 testing ts1 1 tms t est mode select?his is the test mode select f or ieee 1149.1 testing i 1 trst t est reset?his is the reset signal f or ieee 1149.1 testing i 1 user7 user-pro g ramma b le pin pts3 1 rxc recei v e clo c k?r o vides decode recei v e clo c k pts3 1 test t est pin?hen asse r ted, this pin places the AM79C930 d e vice into a nonstandard f acto r y-only test mode i 1 clkin clo c k input to d r i v e bi u , 80188 cor e , an d t ai, supplying net w o r k data r ate in f o r mation i 2 pmx1? p o wer management xtal?2-khz xtal input f or sleep timer re f erence i/xo 1 txc t ransmit clo c k? a y be con gured either as input or output ts1 1 lfpe l o w f requency p o wer ena b le?sed to p o wer up the l o w-frequency section of the t r anscei v er pts1 1 lfclk l o w f requency clo c k? re f erence signal f or the transcei v er synthesi z er ts1 1 llocke l o w f requency synthesi z er lo c k? pro g ramma b le signal pts1 1 hfpe high f requency p o wer ena b le?sed to p o wer up the high-frequency section of the t r anscei v er pts1 1 hfclk high f requency clo c k? re f erence signal f or the transcei v er synthesi z er ts1 2 ants l t , antsl t antenna select?sed to select bet w een two antennas pts1 2 txcmd , txcmd t ransmit command?sed to select the t r ansmit path in the t r anscei v er tp1, pts1 1 txpe t ransmit p o wer ena b le?sed to p o wer up the transmit section of the transcei v er tp1 2 tx d a t a , txd a t a t ransmit data?upplies the t r ansmit data stream to the t r anscei v er tp1, pts1 1 txmod t ransmit modulation ena b le?na b les the modulation of t r ansmit data tp1 1 rxpe recei v e p o wer ena b le?na b les the recei v e function of the t r anscei v er pts1 1 rx d a t a recei v e data?ccepts recei v e data in nrz f o r mat from the transcei v er i 1 fdet f rame detect?ta r t of f r ame delimiter detection indication ts1 1 rxcin recei v e clo c k input?ptional clo c k input that all o ws f or an e xte r nal pll ipu 1 sdclk se r ial data clo c k?lo c k output used to access se r ial pe r iphe r al d e vices pts1 1 sd d a t a se r ial data data?ata pin used to access se r ial pe r iphe r al d e vices pts1 3 sdsel3 sdsel1 se r ial data select?hip select outputs used to select se r ial pe r iphe r al d e vices pts1 1 a ct activity led?utput capa b le of d r iving an led pts2 1 lnk link led?utput capa b le of d r iving an led pts2 1 adref a/d re f erence?n input that can be used to set the analog re f erence v oltage f or the inte r nal a/d co n v e r ter i 7 sar6?ar0 se r ial appr o ximation register?upplies the v alue of the se r ial appr o ximation register used in the a/d co n v e r ter ts1 1 8 AM79C930 preliminary pcmcia pin function summa r y (continued) pcmcia pin summary (conti n ued) output drive r t ypes inpu t t ypes no . of pins pin name pin function pin style 2 adin1? comparator?/d comparator inputs ts1 12 v cc p o wer i 13 gnd ground i 7 user0?ser6 user-de na b le i/o pins with direct accessibility and control throug h tcr and tir registers pts3, pts1 name t ype i ol i oh load tp1 t otem pole 4 ma ? ma 50 pf ts1 t r i- state 4 ma ? ma 50 pf ts2 t r i- state 24 ma ? ma 120 pf pts1 user-pro g ramma b le t r i- state 4 ma ? ma 50 pf pts2 user-pro g ramma b le t r i- state 12 ma ? ma 50 pf pts3 user-pro g ramma b le t r i- state 24 ma ? ma 120 pf od2 open d r ain 24 ma ? ma 120 pf xo xtal ampli er output na na 50 pf name t ype size of pullup size of pulld o wn i input na na ipu input with inte r nal pullup d e vice >50k w na ipd input with inte r nal pulld o wn d e vice na >50k w AM79C930 1 9 preliminary isa plug and pl a y block di a gram jtag control block trst tms/t3 tdi/t1 tdo/t2 rxcin antslt antslt sar6? adin2? adref rxdata sdclk sddata sdsel3? txcmd txcmd txmod txdata txdata rxpe txpe hfpe hfclk lfpe lfclk fdet lnk act rxc ieee 802.11 network interface unit ieee 802.11 mac control unit (80188 core) bus interface unit (isa plug and play) moe mwe ma 16? md 7? xce sce fce la23?7 sa126? sd7? aen bale memr ior iow reset memw iochrdy irq(x) rfrsh pmx2? clk20 test pwrdwn ca16?8 cad 7? int1 ale wr srdy ucs lcs reset drq0 drq1 int0 reset 20183 b -5 20 AM79C930 preliminary isa plug and pl a y connection di a gram notes: pin 1 is marked for orientation. nc = no connection 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 56 57 58 59 60 61 62 98 99 100 101 102 103 104 54 55 53 132 131 130 129 128 127 126 125 124 123 122 144 143 142 141 140 139 138 137 136 135 134 133 121 120 1 19 1 18 1 17 1 16 1 15 1 14 1 13 1 12 1 1 1 1 10 109 108 107 106 105 42 43 44 45 46 47 48 49 50 51 52 40 41 31 4 5 6 7 8 9 10 1 1 1 2 3 28 29 30 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 32 33 34 35 36 37 38 39 la19 sa16 la17 vddm xce ma11 vssm ma9 ma8 ma13 mwe ma14 ma16 ma15 ma12 vddm v cc ma7 ma6 ma5 vssm ma4 ma3 ma2 ma1 ma0 md0 md1 vddm md2 md3 vssm md4 md5 md6 md7 sa15 la20 la21 la23 vddu2 vdd5 avdd adref avss adin2 adin1 pwrdwn antslt txmod vsst txpe fdet v ss txcmd vddt rxcin rxsdata rxpe txdata hfpe hfclk lfpe lfclk vsst txc sar6 sar5 sar4 sar3 sar2 sar1 sar0 sdsel1 vsst sdsel2 vddt sdsel3 addata sdclk lnk vsst act vddu1 irq4 irq5 irq10 vssu1 irq11 irq12 rfrsh v cc tdi trst tms tdo tck pmx1 pmx2 test clk20 pcmcia sd3 sd4 vssp sd5 sd6 sd7 ma10 moe sce fce sd2 sd1 sd0 vssp bale sa0 sa1 aen sa2 la22 sa3 iochrdy sa4 sa7 vddp sa12 v ss reset sa5 sa6 irq9 memw sa14 sa13 sa8 iow ior sa9 sa11 memr sa10 la18 AM79C930 20183 b -6 AM79C930 21 preliminary isa plug and pl a y pin list listed b y pin number pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 la19 37 ma10 73 sd7 109 sar1 2 sa16 38 moe 74 sd6 110 sar2 3 la17 39 sce 75 sd5 111 sar3 4 vddm 40 fce 76 vssp 112 sar4 5 xce 41 sd2 77 sd4 113 sar5 6 ma11 42 sd1 78 sd3 114 sar6 7 vssm 43 sd0 79 pcmcia 115 txc 8 ma9 44 vssp 80 clk20 116 vsst 9 ma8 45 bale 81 test 117 lfclk 10 ma13 46 sa0 82 pmx2 118 lfpe 11 mwe 47 sa1 83 pmx1 119 hfclk 12 ma14 48 aen 84 tck 120 hfpe 13 ma16 49 sa2 85 tdo 121 tx d a t a 14 ma15 50 la22 86 tms 122 rxpe 15 ma12 51 sa3 87 trst 123 rx d a t a 16 vddm 52 iochr d y 88 tdi 124 rxcin 17 v cc 53 sa4 89 v cc 125 vddt 18 ma7 54 sa7 90 rfrsh 126 txcmd 19 ma6 55 vddp 91 irq12 127 v ss 20 ma5 56 sa12 92 irq11 128 fdet 21 vssm 57 v ss 93 vssu1 129 txpe 22 ma4 58 reset 94 irq10 130 vsst 23 ma3 59 sa5 95 irq5 131 txmod 24 ma2 60 sa6 96 irq4 132 ants l t 25 ma1 61 irq9 97 vddu1 133 pwr d wn 26 ma0 62 memw 98 a ct 134 adin1 27 md0 63 sa14 99 vsst 135 adin2 28 md1 64 sa13 100 lnk 136 a vss 29 vddm 65 sa8 101 sdclk 137 adref 30 md2 66 i o w 102 sd d a t a 138 a vdd 31 md3 67 ior 103 sdsel3 139 vdd5 32 vssm 68 sa9 104 vddt 140 vddu2 33 md4 69 sa11 105 sdsel2 141 la23 34 md5 70 memr 106 vsst 142 la21 35 md6 71 sa10 107 sdsel1 143 la20 36 md7 72 la18 108 sar0 144 sa15 22 AM79C930 preliminary isa plug and pl a y pin list listed b y pin name pin name pin no. pin name pin no. pin name pin no. pin name pin no. a ct 98 ma11 6 sa1 47 sdsel2 105 adin1 134 ma12 15 sa10 71 sdsel3 103 adin2 135 ma13 10 sa11 69 tck 84 adref 137 ma14 12 sa12 56 tdi 88 aen 48 ma15 14 sa12 56 tdo 85 ants l t 132 ma16 13 sa13 64 test 81 a vdd 138 ma2 24 sa14 63 tms 86 a vss 136 ma3 23 sa15 144 trst 87 bale 45 ma4 22 sa16 2 txc 115 clk20 80 ma5 20 sa2 49 txcmd 126 fce 40 ma6 19 sa3 51 tx d a t a 121 fdet 128 ma7 18 sa4 53 txmod 131 hfclk 119 ma8 9 sa5 59 txpe 129 hfpe 120 ma9 8 sa6 60 v cc 17 iochr d y 52 md0 27 sa7 54 v cc 89 ior 67 md1 28 sa8 65 vdd5 139 io w 66 md2 30 sa9 68 vddm 4 irq10 94 md3 31 sar0 108 vddm 16 irq11 92 md4 33 sar1 109 vddm 29 irq12 91 md5 34 sar2 110 vddp 55 irq4 96 md6 35 sar3 111 vddt 104 irq5 95 md7 36 sar4 112 vddt 125 irq9 61 memr 70 sar5 113 vddu1 97 la17 3 memw 62 sar6 114 vddu2 140 la18 72 moe 38 sce 39 v ss 57 la19 1 mwe 11 sd0 43 v ss 127 la20 143 pcmcia 79 sd1 42 vssm 7 la21 142 pmx1 83 sd2 41 vssm 32 la22 50 pmx2 82 sd3 78 vssp 44 la23 141 pwr d wn 133 sd4 77 vssp 76 lfclk 117 reset 58 sd5 75 vsst 99 lfpe 118 rfrsh 90 sd6 74 vsst 106 lnk 100 rxcin 124 sd7 73 vsst 116 ma0 26 rx d a t a 123 sdclk 101 vsst 130 ma1 25 rxpe 122 sd d a t a 102 vssu1 93 ma10 37 sa0 46 sdsel1 107 xce 5 AM79C930 23 preliminary isa plug and pl a y pin summa r y no . of pins pin name pin function pin style 7 la23?a17 isa upper address b us lines i 17 sa16?a0 isa l o wer address b us lines i 8 sd7?d0 isa data b us lines ts2 1 reset reset input i 1 memr memo r y read?sed to ena b le the output d r i v ers of the AM79C930 d e vice f or isa b us memo r y read accesses i 1 memw memo r y w r ite?sed to indicate that the current isa b us cycle is a memo r y w r ite access i 1 aen address ena b le?sed to indicate that the current isa b us i/o address is v alid i 1 bale bus address latch ena b le?sed to indicate that the isa address lines are v alid i 1 iochr d y i/o channel ready?sed to del a y the te r mination of the current isa b us cycle ts2 1 ior i/o read?his signal is asse r ted b y the isa host system when e v er an i/o read ope r ation occurs i 1 io w i/ o w r ite?his signal is asse r ted b y the isa host system when e v er an i/o w r ite ope r ation occurs i 6 irq4, 5, 9, 10, 11, 12 inter r upt request?his line is asse r ted when the AM79C930 d e vice needs se r vicing from the soft w are pts3/od2 1 rfrsh refresh?ndicates that the current isa b us cycle is a refresh ope r ation i 1 pcmcia pcmcia mode?elects pcmcia or isa plug and pl a y mode i 1 pwr d wn p o werd o wn?ndicates that d e vice is in the p o wer d o wn mode tp1 17 ma16? memo r y address bus?hese lines are used to address locations in the flash d e vic e , the sram d e vic e , and an e xtra pe r iphe r al d e vice that are contained within an AM79C930-based design tp1 8 md7? memo r y data bus?hese lines are used to w r ite and read data to/from flash, sram, and/or an e xtra pe r iphe r al d e vice within an AM79C930-based design ts1 1 fce flash chip ena b le?his signal becomes asse r ted when the flash d e vice has been addressed b y either the 80188 core of the AM79C930 d e vice or b y the soft w are through the pcmcia inter f ace tp1 1 sce sram chip ena b le?his signal becomes asse r ted when the sram d e vice has been addressed b y either the 80188 core of the AM79C930 d e vice or b y the soft w are through the pcmcia inter f ace tp1 1 xce extra chip ena b le?his signal becomes asse r ted when the e xtra pe r iphe r al d e vice has been addressed b y the 80188 core of the AM79C930 d e vice (xce is not accessi b le through the system inter f ace) tp1 1 moe memo r y output ena b le?his signal becomes asse r ted du r ing reads of d e vices located on the memo r y inter f ace b us tp1 1 mwe memo r y w r ite ena b le?his signal becomes asse r ted du r ing w r ites to d e vices located on the memo r y inter f ace b us tp1 1 tck t est clo c k?his is the clo c k signal f or ieee 1149.1 testing i 1 tdi t est data in?his is the data input signal f or ieee 1149.1 testing i 1 tdo t est data out?his is the data output signal f or ieee 1149.1 testing ts1 1 tms t est mode select?his is the test mode select f or ieee 1149.1 testing i 1 trst t est reset?his is the reset signal f or ieee 1149.1 testing i 1 test t est pin?hen asse r ted, this pin places the AM79C930 d e vice into a non- ieee 1149.1 test mode i 1 clkin clo c k input to d r i v e bi u , 80188 cor e , an d t ai, supplying net w o r k data r ate in f o r mation i 2 pmx1? p o wer management xtal?2-khz xtal input f or sleep timer re f erence i/xo 24 AM79C930 preliminary isa plug and pl a y pin summa r y (continued) output drive r t ypes inpu t t ypes no . of pins pin name pin function pin style 1 txc t ransmit clo c k? a y be con gured either as input or output ts1 1 lfpe l o w f requency p o wer ena b le?sed to p o wer up the l o w-frequency section of the t r anscei v er pts1 1 lfclk l o w f requency clo c k? re f erence signal f or the transcei v er synthesi z er ts1 1 hfpe high f requency p o wer ena b le?sed to p o wer up the high-frequency section of the t r anscei v er pts1 1 hfclk high f requency clo c k? re f erence signal f or the transcei v er synthesi z er ts1 1 ants l t antenna select?sed to select bet w een two antennas pts1 1 txcmd t ransmit command?sed to select the t r ansmit path in the t r anscei v er tp1 1 txpe t ransmit p o wer ena b le?sed to p o wer up the transmit section of the transcei v er tp1 1 tx d a t a t ransmit data?upplies the t r ansmit data stream to the t r anscei v er tp1 1 txmod t ransmit modulation ena b le?na b les the modulation of t r ansmit data tp1 1 rxpe recei v e p o wer ena b le?na b les the recei v e function of the t r anscei v er pts1 1 rx d a t a recei v e data?ccepts recei v e data in nrz f o r mat from the transcei v er i 1 fdet f rame detect?ta r t of f r ame delimiter detection indication ts1 1 rxcin recei v e clo c k input?ptional clo c k input that all o ws f or an e xte r nal pll ipu 1 sdclk se r ial data clo c k?lo c k output used to access se r ial pe r iphe r al d e vices pts1 1 sd d a t a se r ial data data?ata pin used to access se r ial pe r iphe r al d e vices pts1 3 sdsel3 sdsel1 se r ial data select?hip select outputs used to select se r ial pe r iphe r al d e vices pts1 1 a ct activity led?utput capa b le of d r iving an led pts2 1 lnk link led?utput capa b le of d r iving an led pts2 1 adref a/d re f erence?n input that can be used to set the analog re f erence v oltage f or the inte r nal a/d co n v e r ter i 7 sar6?ar0 se r ial appr o ximation register?upplies the v alue of the se r ial appr o ximation register used in the a/d co n v e r ter ts1 2 adin1? comparator?/d comparator inputs ts1 12 v cc p o wer i 13 gnd ground i name t ype i ol i oh load tp1 t otem pole 4 ma ? ma 50 pf ts1 t r i- state 4 ma ? ma 50 pf ts2 t r i- state 24 ma ? ma 120 pf pts1 user-pro g ramma b le t r i- state 4 ma ? ma 50 pf pts2 user-pro g ramma b le t r i- state 12 ma ? ma 50 pf pts3 user-pro g ramma b le t r i- state 24 ma ? ma 120 pf od2 open d r ain 24 ma ? ma 120 pf xo xtal ampli e r output na na name t ype size of pullup size of pulld o wn i input na na ipu input with inte r nal pullup d e vice >50k w na ipd input with inte r nal pulld o wn d e vice na >50k w p r e l i m i n a r y amd 25 AM79C930 pin descriptions pins with internal pull up or pull down devices several pins of the AM79C930 device include internal pull up or pull down devices. with the exception of the reset pin, these pins are fully programmable as inputs or outputs when the pcmcia mode has been selected. a subset of these pins is programmable when the isa plug and play mode has been selected. these pins will come up after reset in the high impedance state with the pull up or pull down device actively determining the value of the pin, unless an external driving source overdrives the pull up or pull down device. vinitdn bit (mir9[2]) is used to turn off all pull up and pull down devices. the following list indicates those pins that contain pull up and pull down devices: pcmcia mode internal device size of internal pin name type device user[6]/irq5 pull up > 100k w user[5]/irq4 pull up > 100k w user[4]/la17 pull up > 100k w user[3]/sa16 pull up > 100k w user[2]/la19 pull up > 100k w user[1]/irq12 pull down > 100k w user[0]/rfrsh pull down > 100k w llocke/sa15 pull down > 100k w antslt /la23 pull up > 100k w txdata /la20 pull up > 100k w txcmd/la21 pull down > 100k w rxc/irq10 pull up > 100k w user7/irq11 pull up > 100k w lfpe pull up > 100k w hfpe pull up > 100k w rxpe pull up > 100k w antslt pull down > 100k w txcmd pull up > 100k w txpe pull up > 100k w sdclk pull up > 100k w sddata pull up > 100k w sdsel [3] pull up > 100k w sdsel [2] pull up > 100k w sdsel [1] pull up > 100k w act pull up > 100k w lnk pull up > 100k w txmod pull up > 100k w stschg /bale pull up > 100k w txc pull up > 100k w following the reset operation, the AM79C930 firm ware or driver software should appropriately program the d bits of tir and tcr registers, and then set the fn and en bits of tir and tcr registers to set the values and directions of each of these programmable pins. once these operations have been performed, the soft ware should then program the initdn bit of mir9 in or der to disable all of the pull up and pull down devices. unused programmable pins should be programmed for output mode, or may be left in the default high imped ance state if an external pull down or pull up device is left connected to the pin. unused programmable pins must not be programmed for input mode with no external source (pull device or driver) connected and the initdn bit of mir9 set to a 1, since this could lead to unaccept able levels of power consumption by the AM79C930 de vice. for more information on programmable pins, see the multi function pins section. configuration pins pcmcia pcmcia/isa bus interface select input the value of this pin will asynchronously determine the operating mode of the AM79C930 device, regardless of the state of the reset pin and regardless of the state of the clkin pin. if the pcmcia pin is tied to vcc, then the AM79C930 controller will be programmed for pcmcia bus mode. if the pcmcia pin is tied to vss, then the AM79C930 controller will be programmed for isa plug and play bus interface mode. amd p r e l i m i n a r y 26 AM79C930 the functionality of the following pins is determined, at least in part, by the connection of the pcmcia pin: pcmcia mode isa plug and play mode pin name pin name user6 user6/irq5 user5 user5/irq4 user4 la17 user3 sa16 user2 la19 user1 user1/irq12 user0 rfrsh a[14:0] sa[14:0] llocke sa15 d[7:0] sd[7:0] ce1 la18 oe memr we memw reg aen txdata la20 txcmd la21 inpack la22 antslt la23 wait iochrdy stschg bale iord ior iowr iow ireq irq9 rxc rxc/irq10 user7 user7/irq11 host system interface pins pcmcia bus interface a14C0 address bus input signals a0 through a14 are address-bus-input lines. signal a0 is always used because the data interface to the AM79C930 is only 8-bits wide. ce1 card enable input ce1 is an active low card enable input signal. ce1 is used to enable even-numbered word address bytes. a0 is used to select between the even and odd numbered bytes within the addressed word. d7C0 data bus input/output signals d7 through d0 are the bidirectional data bus for pcmcia. the most significant bit is d7. oe output enable input oe is an active low-output-enable input signal. oe is used to gate memory read data from the AM79C930 de- vice onto the pcmcia data bus. oe should be deas- serted during memory write cycles to the AM79C930 device. oe is used for common memory accesses and attribute memory accesses. inpack input acknowledge output the inpack signal is an active low signal. inpack is asserted when the AM79C930 device is selected and the AM79C930 device can respond to an i/o read cycle at the address currently on the address bus. this signal is used by the host to control the enable of any input data buffer between the card and the cpu. this signal will be inactive until the card is configured. iord i/o read input iord is an active low signal. iord is asserted by the host system to indicate to the AM79C930 device that a read from the AM79C930's i/o space is being per- formed. the AM79C930 device will not respond to the iord signal until it has been configured for i/o opera- tion by the system. iowr i/o write input iowr is an active low signal. iowr is asserted by the host system to indicate to the AM79C930 device that a write to the AM79C930's i/o space is being performed. the AM79C930 device will not respond to the iowr sig- nal until it has been configured for i/o operation by the system. ireq interrupt request output ireq is an active low signal. ireq is asserted by the AM79C930 device to indicate to the host that software service is required. ireq can operate in the pulse mode or level mode of operation as defined in the pcmcia specification. in pulse mode of operation, an interrupt is signaled by the AM79C930 device by asserting a low- going pulse of at least 0.5 microseconds ( m s). in pulse mode of operation, the inactive state (i.e., high output) is driven, not floated. in level mode of operation, an in terrupt is signaled by the AM79C930 device by assert ing a low level. in level mode of operation, the inactive state (i.e., high output) is driven, not floated. p r e l i m i n a r y amd 27 AM79C930 function mode reg ce1 iord iowr a0 oe we d7C0 standby mode x h x x x x x high-z common memory read even byte h l h h l l h even byte common memory read odd byte h l h h h l h odd byte common memory write even byte h l h h l h l even byte common memory write odd byte h l h h h h l odd byte attribute memory read even byte l l h h l l h even byte attribute memory read odd byte l l h h h l h odd byte attribute memory write even byte l l h h l h l even byte attribute memory write odd byte l l h h h h l odd byte i/o read even byte l l l h l h h even byte i/o read odd byte l l l h h h h odd byte i/o write even byte l l h l l h h even byte i/o write odd byte l l h l h h h odd byte reg attribute memory select input reg is an active low-input signal that selects among at- tribute memory and common memory in the AM79C930 device and the AM79C930-based pcmcia card. when reg is asserted, then the current access is to attribute memory or i/o. when reg is not asserted, then the cur- rent access is to common memory. reset reset input reset is an active high-input signal that clears the card configuration option register ccor) and places the AM79C930 device into an unconfigured (pcmcia- memory-only interface) state. this pin also causes a reset to be asserted to each of the AM79C930 core function units (i.e., pcmcia interface, cpu, and trans- ceiver attachment interface). stschg status change output the stschg signal is an active low signal. stschg as implemented in the AM79C930 device is only used for the pcmcia wakeup indication. the changed bit and the sigchg bit of the card configuration and status register (ccsr) are not supported by the AM79C930 device. the pin replacement register is not supported by the AM79C930 device. wait extend bus cycle output the wait signal is an active low signal. wait is as- serted by the AM79C930 device to delay completion of the access cycle currently in progress. we write enable input we is an active low write-enable input signal. we is used to strobe memory write data into the AM79C930 device from the pcmcia data bus. we should be deas- serted during memory read cycles to the AM79C930. we is used for common memory accesses and attrib- ute memory accesses. isa (ieee p996) bus interface la23C17, sa16C0 address bus input signals sa0 through sa16 and la17 through la23 are address-bus-input lines which enable direct address of up to 16 mbytes of memory space in an isa-based AM79C930 design. signal sa0 is always used, because the data interface to the AM79C930 is only 8-bits wide. sd7C0 data bus input/output signals sd7 through sd0 are the bidirectional data bus for isa. the most significant bit is sd7. aen address enable input aen is driven low by the isa host to indicate when an i/o address is valid. bale bus address latch enable input bale is driven by the isa host to indicate when the ad- dress signal lines are valid. iochrdy i/o channel ready output the iochrdy signal is deasserted by the AM79C930 device at the beginning of a memory access in order to delay completion of the memory access cycle then in progress. the iochrdy signal is reasserted by the AM79C930 device when the memory access is completed. amd p r e l i m i n a r y 28 AM79C930 ior i/o read input the ior signal is made active by the isa host in order to read data from the AM79C930 device's i/o space. iow i/o write input the iow signal is made active by the isa host in order to write data to the AM79C930 device's i/o space. memr memory read input the memr signal is made active by the isa host in order to read data from the AM79C930 device's memory space. memw memory write input the memw signal is made active by the isa host in order to write data to the AM79C930 device's memory space. irq[4,5,9C12] interrupt request output irq[x] is asserted by the AM79C930 device to indicate to the host that software service is required. irq[x] is held at the inactive level when no interrupt is requested. only one of the six irq[x] lines may be selected for use at any one time. irq[x] outputs may be programmed for edge or level operation. edge or level programming is part of the isa plug and play initialization procedure. when edge programming has been selected, then the selected irq[x] pin is driven to a high level to indicate an active interrupt request, and the selected irq[x] pin is driven to a low level to indicate an inactive interrupt re- quest. when level programming has been selected, then the selected irq[x] pin is driven to a low level and the selected irq pin is floated to indicate an inactive interrupt request (i.e., open drain operation). unused (i.e., unselected) irq[x] lines will be held in a high impedance state, even when interrupt service is requested. reset reset input reset is an active high input signal. when driven to a high level, reset causes the AM79C930 device to immediately place all isa bus outputs into a high imped- ance state. this pin also causes a reset to be as- serted to each of the AM79C930 core function units (i.e., isa interface state machine, 80188, and transceiver attachment interface). rfrsh refresh input the rfrsh signal is made active by the isa host to in- dicate that the current bus cycle is a refresh operation. memory interface pins ma16C0 memory address bus output signals ma0 through ma16 are address-bus-output lines which enable direct address of up to 128 kbytes of sram memory and 128 kbytes of flash memory in a AM79C930-based application. the AM79C930 device will drive these signals to access memory locations within the sram or the flash memory. fce flash memory chip enable output fce is an active low chip enable output signal. fce is used to activate the flash memory device's control logic and input buffers during accesses on the memory interface bus. md7C0 memory data bus input/output signals md7 through md0 are the bidirectional data bus for the sram and the flash memory. the most signifi- cant bit is md7. moe memory output enable output moe is an active low output that is used to gate the out- puts of the sram and flash memory device's during read cycles. sce sram chip enable output sce is an active low chip enable output signal. sce is used to activate the sram device's control logic and input buffers during accesses on the memory interface bus. mwe memory write enable output mwe is an active low output that is used to latch address and data information in the sram and flash memory devices during write cycles. address information for sram and flash memory write cycles is valid on the ma16C0 pins at the falling edge of mwe . data informa- tion for sram and flash memory write cycles is valid on the md7C0 pins at the rising edge of mwe . xce extra chip enable output xce is an active low chip enable output signal. xce is used to activate a peripheral device's control logic and input buffers during accesses on the memory interface bus. xce is activated by appropriate signaling from the 80188 embedded core. xce may not be activated through the system interface. sixteen bytes of address range are allotted for use with the xce signal. p r e l i m i n a r y amd 29 AM79C930 clock pins clkin system clock input clkin is the clock input for the AM79C930 device's logic functions. clkin is used to drive the clkin input of the embedded 80188 core. the biu section uses the clkout signal from the 80188 embedded core as a reference. the register interface portions of the tai use the clkin signal as a reference. the tai uses a divided version of this clock to obtain a reference clock for data transmission, where the divisor value is selectable through a register; this allows different data rates to be set. the tai dpll clock recovery circuit will use a refer ence clock that is 20 times the selected data rate, when ever the eclk bit of the receiver configuration register (tcr3) is set to a 0. this dpll reference clock is also derived from the clkin signal. when the eclk bit is set to 1, the tai dpll is not used, and the incoming receive data stream is clocked with the rxcin signal. the highest frequency allowed at the clkin in put is 40 mhz. pmx[1-2] power management crystal input/output pmx[1-2] are the reference crystal inputs for the clock that drives the power management logic. the nominal frequency for this crystal input is 32 khz. rxcin receive clock in input rxcin is the reference clock input for the receive data stream entering the AM79C930 device when the eclk bit of tcr2 is set to a 1. rising edges of the rxcin input will mark valid sample points for the data arriving at the rxdata input. rxc receive clock out output rxc is the reference clock output for the receive data stream that is derived either from the dpll or from the rxcin pin, depending on the selected AM79C930 de vice configuration. this clock is provided for test pur poses only. this function is only available when the AM79C930 device is programmed for the pcmcia mode of operation. txc transmit clock input/output txc is the clock reference for data transmission at the network interface. some systems may require that the AM79C930 device deliver the transmit data with a clock for reference. in such systems, the txc pin may be configured as an output and the txc signal will be generated by the AM79C930 device as a derivative from the clkin input. txdata will change on falling edges of txc, allowing ample setup and hold time for valid sampling of txdata with the rising edge of txc. some systems may require that the AM79C930 device deliver the transmit data according to a clock reference that is external to the AM79C930 device. in such sys tems, the txc pin may be configured as an input. txdata will change on falling edges of txc, allowing ample setup and hold time for valid sampling of txdata with the rising edge of txc. system management pins pwrdwn power down output pwrdwn is an active high output that indicates that the AM79C930 device has been placed into a low power mode to conserve power. while pwrdwn is asserted, the internal clock that is routed to the 80188 embedded core and the network interface (tai section) has been halted. pcmcia ccrs and sirs are still active while in the low power mode. user[0-6] user definable pins input/output user[0-6] are pins that are controlled directly through tir and tcr registers. these pins may serve as out puts, inputs or as i/o through the use of high impedance control and data bits in tir and tcr registers. these pins are available only in pcmcia mode. note: some of the tai interface pins are similarly programmable, thereby allowing some user defined functionality when using the isa plug and play mode of operation. tai interface pins antslt antenna select output antslt is an active high output that indicates to the transceiver which antenna should be utilized for both transmission and reception. antslt allows for selec- tion among two possible antennas. antslt antenna select output antslt is an active low output that is the logical inverse of the antslt output. this signal is only available when the AM79C930 device is configured for the pcmcia mode of operation. fdet frame detect output fdet is an active low output that indicates when the AM79C930 device has located the start of frame de- limiter in the receive or transmit data stream. this signal amd p r e l i m i n a r y 30 AM79C930 is deasserted when the reset pin is issued or the crc reset bit is set to 1 (sir0); when the txs bit is set to 1 (tir8) or the rxs bit is set to 1 (tir16); when txres bit set to 1 (tir8), or the rxres bit is set to 1 (tir16), or the sres bit is set to 1 (tir0). hfclk high frequency clock output hfclk provides a reference clock for a transceiver syn thesizer. the clock rate is equal to the clock rate of the clkin signal when the clkgt20 bit of mir9 is set to 0, and is equal to one half the clock rate of the clkin sig nal when the clkgt20 bit of mir9 is set to 1. no phase relationship to clkin is guaranteed. hfclk will be low whenever the hfpe signal is inactive. hfpe high frequency power enable output hfpe is an active low output that is used to power up the high-frequency vco section of the transceiver. this pin is directly controllable through a tai register and is also programmable as an i/o with read capability. lfclk low frequency clock output lfclk provides a reference clock for a transceiver syn- thesizer. the clock rate is equal to the clock rate of the clkin signal when the clkgt20 bit of mir9 is set to 0, and is equal to one half the clock rate of the clkin sig- nal when the clkgt20 bit of mir9 is set to 1. no phase relationship to clkin is guaranteed. lfclk will be low whenever the lfpe signal is inactive. lfpe low frequency power enable output lfpe is an active low output that is used to power up the low-frequency synthesizer section of the transceiver. this pin is directly controllable through a tai register and is also programmable as an i/o with read capability. llocke synthesizer lock input llocke is a general-purpose input that can be used to convey a transceiver's synthesizer lock signal to the 80188 embedded controller. the value of the llocke pin is readable at a register bit in the tir register space. rxdata receive data input rxdata is an input that accepts the serial bit stream for reception, including preamble, sfd, phy header, mac header, data and fcs field. the rxdata input stream is expected to be nrz data. clock recovery is per- formed internal to the AM79C930 device. if an external pll is used for clock recovery, then the rxdata input will expect valid data at rising edges of the rxcin input. external versus internal pll use is determined through the setting of the eclk bit in tcr2. rxpe receiver power enable output rxpe is an active low output that is used to power up the receive section of the transceiver. this pin is directly controllable through a tai register and is also program- mable as an i/o with read capability. txcmd transmit command output txcmd is an active low output that is used to enable the transceiver's transmission onto the medium. when txcmd is low, the transceiver should enable its trans- mission function and disable its receive function. when txcmd is high, the transceiver should disable its transmission function and return to receive functionality. this pin is directly controlled by the transmit state machine in the tai and the txcmd bit of tir11. the timing of the txcmd signal is programmable from a tai register. the polarity of this pin is programmable from a tai register. txcmd transmit command output txcmd is an active high output that is the logical in- verse of the txcmd output. this signal is only available when the AM79C930 device is configured for the pcmcia mode of operation. txdata transmit data output txdata is an output that provides the serial bit stream for transmission, including preamble, sfd, phy header, mac header, data and fcs field, or a subset thereof. data delivered from the mac to the transceiver is valid at the rising edge of txc and changes on the fall- ing edge of txc. the value of the txdata pin is pro- grammable to 1, 0, or last bit transmitted whenever the transmit circuit is idle and during ramp up and ramp down of the transceiver's transmit circuits. txdata transmit data output txdata is an output that is the logical inverse of the txdata output. this signal is only available when the AM79C930 device is configured for the pcmcia mode of operation. the value of the txdata pin is 0 when- ever the transmit circuit is idle and during ramp up and ramp down of the transmitter. p r e l i m i n a r y amd 31 AM79C930 txmod transmit modulation enable output txmod is an active low output that is used to enable the transmit modulation function of the attached trans- ceiver. this pin is directly controlled by the transmit state machine in the tai and the txmod bit of tir11. the timing of the txmod signal is programmable from a tai register. the polarity of this pin is programmable from a tai register. txpe transmit power enable output txpe is an active low output that is used to enable the transceiver's transmission amplifier. when txpe is low, the transceiver should enable its transmission amplifier. when txpe is high, the transceiver should disable its transmission amplifier. this pin is directly controlled by the transmit state machine in the tai and the txpe bit of the tir11. the timing of the txmod signal is program- mable from a tai register. the polarity of this pin is pro- grammable from a tai register. user7 user7 input/output user7 is a pin that may be directly controlled through tir and tcr register locations. other pins act activity led output act is an active low open collector output that is directly controllable through a tai register. this pin is capable of sinking the 12 ma necessary to drive a typical indicator led. this pin is directly controllable through a tai regis- ter and is also programmable as an i/o with read capa- bility. this pin may also be programmed to actively drive high output values. when an led is connected to this pin, then proper operation of this output requires a pull-up device to be connected externally. adref a/d reference input adref is a single-ended analog input that is used by the a/d conversion circuit. adref is the reference volt- age that is fed to the resistor ladder of the d/a portion of the a/d circuit. adref is used to determine the range of sensitivity of the a/d circuit. the recommended value for adref is 1.25 to 1.75 v. note that adref is volt- age-doubled before being used for internal a/d refer- ence. for example, an adref value of 1.75 v will mean that the a/d will give a max digital output value for an adin input of 3.5 v or higher. adin[1C2] a/d sample inputs input/output adin[1C2] are inputs that accept single-ended analog input values for conversion by the internal AM79C930 a/d converter. only one input will be sampled at any time for conversion by the internal AM79C930 device's a/d circuit. the input that will be converted by the a/d circuit is determined by the setting of the srcs bit of the antenna diversity and a/d control register in the tai (tir26). lnk link led output lnk is an active low open collector output that is directly controllable through a tai register. this pin is capable of sinking the 12 ma necessary to drive a typical indicator led. this pin is directly controllable through a tai regis- ter and is also programmable as an i/o with read capa- bility. this pin may also be programmed to actively drive high output values. when an led is connected to this pin, then proper operation of this output requires a pull-up device to be connected externally. pwrdwn powerdown output pwrdwn is an output that becomes active (high) when the AM79C930 device enters the power down mode. this pin can be used to power down other sec- tions of a AM79C930-based system design. sar[6C0] serial approximation register input/output sar[6C0] are outputs that are used to deliver the value of the internal a/d converter for use external to the AM79C930 device. these pins are directly controllable through a tai register and are also programmable as i/o pins with read capability. sdclk serial device clock output sdclk is an output that is used to clock data on the sddata output pin. this pin may be used in combina- tion with the sddata and sdsel output pins in order to create an i 2 c serial device interface. this pin is directly controllable through a tai register and is also program- mable as an i/o with read capability. sddata serial device data input/output sddata is an i/o pin that may be used in conjunction with the sdclk and sdsel pins in order to create an i 2 c serial device interface. this pin is directly controlla- ble through a tai register and is also programmable as an i/o with read capability. sdsel [1C3] serial device select output sdsel [1C3] are output pins that may be used in con- junction with the sdclk and sdsel pins in order to cre- ate an i 2 c serial device interface. these pins are directly controllable through a tai register and are also pro- grammable as i/o pins with read capability. amd p r e l i m i n a r y 32 AM79C930 ieee 1149.1 test access port pins tck test clock input tck is the clock input for the boundary scan test mode operation. tck frequency may be as high as 10 mhz. tck does not have an internal pull-up resistor and must be connected to a valid ttl or cmos level at all times. tck must not be left unconnected. tdi test data input input tdi is the test data input path to the AM79C930 device. if left unconnected, this pin has a default value of high. tdo test data output output tdo is the test data output path from the AM79C930 de- vice. tdo is tri-stated when the jtag port is inactive. tms test mode select input tms is a serial input bit stream is used to define the spe- cific boundary scan test to be executed. if left uncon- nected, this pin has a default value of high. trst test reset input when asserted, trst will asynchronously reset the ieee 1149.1 state. the reset state of the ieee 1149.1 state machine is ffh. test pin test test input the test pin should be tied high and is reserved for internal factory test only. power supply pins analog power supply pins avdd analog power (1 pin) power there is one analog 5 v supply pin. this supply pin pro- vides power to the analog section of the AM79C930 de- vice. this pin must always be connected to 5 v, unless the a/d function of the device is not required. if the a/d function of the device is not required, then this pin may be connected to either a 5 v supply or to a 3.3 v supply. note: a/d must be disabled. however, all analog power pins (avdd and vdd5) must be connected to the same supply voltage. special attention should be paid to the printed circuit board layout to avoid excessive noise on the avdd line. avss analog ground (1 pin) ground there is one analog ground pin. this ground pin pro- vides ground reference to the analog section of the AM79C930 device. this pin must always be connected to a ground supply. special attention should be paid to the printed circuit board layout to avoid excessive noise on the avss line. vdd5 a/d power (1 pins) power there is one a/d power supply pin. this pin provides power to the a to d converter circuit. this pin must always be connected to a 5 v supply unless the a/d function of the device is not required. if the a/d function of the device is not required, then this pin may be con- nected to either a 5 v supply or to a 3.3 v supply. how- ever, all analog power pins (avdd and vdd5) must be connected to the same supply voltage. special attention should be paid to the printed circuit board layout to avoid excessive noise on the vdd5 line. digital power supply pins vddt transceiver power (2 pins) power there are two transceiver interface power supply pins. these pins provide power to the transceiver interface buffers and drivers on pins 98 through 133. these pins may be connected to either a 5.0 v supply or a 3.3 v sup- ply, but both of these pins must be connected to the same supply voltage. vsst transceiver ground (4 pins) ground there are four transceiver interface ground pins. these pins provide ground reference to the transceiver interface buffers and drivers on pins 98 through 133. in both 5 v and 3 v systems, these pins should be con- nected to a ground supply. vcc core logic power (2 pins) power there are two core logic power supply pins. these pins provide power to the core logic and must always be less than or equal to vddt, vddu1, vddu2, vddp, and vddm. p r e l i m i n a r y amd 33 AM79C930 vddt, vddu1, vddu2, vddp, acceptable vcc vddm avdd, vdd5 combination 5 v all at 5 v both at 5 v yes 3 v all at 5 v both at 5 v yes 3 v any combination both at 5 v yes of 3 v and 5 v 3 v all at 3 v both at 5 v yes 5 v all at 3 v both at 5 v no 5 v any combination both at 5 v no of 3 v and 5 v 5 v all at 5 v any no combination of 3 v and 5 v also, avdd and vdd5 must be tied to 5 v, if a/d func- tion is required. vddt, vddu1, vddu2, vddp, and vddm do not have to have the same voltage. if vcc = 3 v, any combination of 5 v or 3 v for vddxx will work. vss core logic ground (2 pins) ground there are two core logic ground pins. these pins provide ground reference to the core logic. in both 5 v and 3 v systems, these pins should be connected to a ground supply. vddu1 user pin power (1 pin) power there is one vddu1 power supply pin. this pin pro- vides power to the buffers and drivers on pins 84 through 96. this pin may be connected to either a 5 v supply or to a 3.3 v supply. vssu1 core logic ground (1 pin) ground there is one vssu1 ground pin. this pin provides ground reference to the buffers and drivers on pins 84 through 96. in both 5 v and 3 v systems, this pin should be connected to a ground supply. vddu2 user pin power (1 pin) power there is one vddu2 power supply pin. this pin pro- vides power to the buffers and drivers on pins 1 through 3 and pins 139 through 144. this pin may be connected to either a 5 v supply or to a 3.3 v supply. vddp pcmcia power (1 pin) power there is one pcmcia power supply pin. this pin pro- vides power to pcmcia and power management crys- tal buffers and drivers on pins 4l through 83. this pin may be connected to either a 5 v supply or to a 3.3 v supply. vssp pcmcia ground (2 pins) ground there are two pcmcia ground pins. these pins provide ground reference to the pcmcia and power manage- ment crystal buffers and drivers on pins 41 through 83. in both 5 v and 3 v systems, these pins should be con- nected to a ground supply. vddm memory interface power (3 pins) power there are three memory interface power supply pins. these pins provide power to the memory interface buff- ers and drivers on pins 4 through 40. these pins may be connected to either a 5.0 v supply or to a 3.3 v supply, but all three of these pins must be connected to the same supply voltage. vssm memory interface ground (3 pins) ground there are three memory interface ground pins. these pins provide ground reference to the memory interface buffers and drivers on pins 4 through 40. in both 5 v and 3 v systems, these pins should be connected to a ground supply. multi-function pins the AM79C930 device includes a number of pins which have multiply-defined functions. the various functions assigned to each of these pins is determined through both device pin settings and through individual register bit settings. this section explains the functional modes of each of the multi-function pins and gives tables that indicate the proper programming for each pin. pins in this section are listed by pin number. where the pcmcia pin is not listed in a table, it can be inferred that the setting of the pcmcia pin has no influ- ence on the pin values. under the column where pin directions are given in the table, i = input (high impedance), o = output (totem pole), od = open drain. under the column where pin data is given in the table, when the pin direction is given as output, then the pin data column indicates the source for the pin's output value. under the column where pin data is given in the table, when the pin direction is given as input, then the pin data column will indicate na, since the source for the pin value is external. note that when any pin is configured for an input function, the pin value is almost always available at the pin data register. a note following each table indicates the availability of the pin data with re- spect to the pin data register bit. note that in almost all cases, the pin data register bit will always read the pin value, even if the pin is configured amd p r e l i m i n a r y 34 AM79C930 for an output function. this means that there are con- figurations for which a read of the pin data register bit will not reflect what has most recently been written to the pin data register bit ( i.e., if a pin is configured as an output with its data source as some internal circuit, then the user may write the pin data bit with a given value, and a read of this same bit will yield the output function value, which may not necessarily match the value just written to the data bit). this functionality is given as a note following each table. also note that for a few pins, the read and write locations for the pin data are in different places. pin 1: user2/la19 the user2/la19 pin may be configured for input op- eration, output operation, or isa la19 operation accord- ing to the following table: user2/ user2/ pcmcia user2en la19 la19 pin tcr14[2] pin direction pin data 0x i na (la19 input function) 10 i na 1 1 o tir29[2] note that a read of the userdt[2] bit (tir29[2]) will al- ways give the current user2/la19 pin value, regard- less of pin configuration setting. pin 2: user3/sa16 the user3/sa16 pin may be configured for input op- eration, output operation, or isa sa16 operation ac- cording to the following table: user3/ user3/ pcmcia user3en sa16 sa16 pin tcr14[3] pin direction pin data 0x i na (sa16 input function) 10 i na 1 1 o tir29[3] note that a read of the userdt[3] bit (tir29[3]) will al- ways give the current user3/sa16 pin value, regard- less of pin configuration setting. pin 3: user4/la17 the user4/la17 pin may be configured for input op- eration, output operation, or isa la17 operation accord- ing to the following table: user4/ user4/ pcmcia user4en la17 la17 pin tcr14[4] pin direction pin data 0x i na (la17 input function) 10 i na 1 1 o tir29[4] note that a read of the userdt[4] bit (tir29[4]) will al- ways give the current user4/la17 pin value, regard- less of pin configuration setting. pin 45: stschg /bale the stschg /bale pin may be configured for input op- eration, output operation, or isa bale operation ac- cording to the following table: stschg / stschg / pcmcia stschgfn bale bale pin tcr15[0] pin direction pin data 0x i na (bale input function) 1 0 o mir9[0] 1 1 o mir9[0] or ccsr[4] mir9[0] is the stschgd bit. in pcmcia mode, stschgd basically acts like a unmasking function for the stschg pin. stschgd can be used to prevent the wakeup signal from the pcmcia card configura- tion and status register from being signaled on the stschg pin. note that if stschgfn is set to 1 and stschgd is set to a 0, then the stschg pin will al- ways be deasserted (i.e., it will be masked). with stschgfn=1, writing a 1 to the stschgd bit will unmask the wakeup status and allow it to be applied to the stschg pin. note that the stschgd bit is automatically reset to 0 whenever the wakeup bit of the pcmcia card con- figuration and status register is reset to 0. therefore, the unmask bit (stschgd) needs to be set to unmask (=1) for each new use of the wakeup signal. when stschgfn is set to 0, then the stschgd bit will become an inverted source for the stschg pin value. note that a read of the stschgd bit (mir9[0]) will al- ways give the inverse of the current stschg /bale pin value, regardless of pin configuration setting. pin 90: user0/ rfrsh the user0/ rfrsh pin may be configured for input op- eration, output operation, or isa rfrsh operation ac- cording to the following table: user0/ user0/ pcmcia user0en rfrsh rfrsh pin tcr14[0] pin direction pin data 0x i na ( rfrsh input function) 10 i na 1 1 o tir29[0] p r e l i m i n a r y amd 35 AM79C930 note that a read of the userdt[0] bit (tir29[0]) will al- ways give the current user0/rfrsh pin value, regard- less of pin configuration setting. pin 91: user1/irq12/extcts/exint188 the user1/irq12 pin may be configured for input operation, output operation, or isa irq12 operation ac- cording to the following table: user1/ user1/ pcmcia user1en irq select irq type irq12 irq12 pin tcr14[1] pnpx70 pnpx71 pin direction pin data 0 x ch 2h o irq12 0 x ch 1h od irq12 00 1 ch x i na 01 1 ch x o tir29[1] 10xxina 1 1 x x o tir29[1] note that a read of the userdt[1] bit (tir29[1]) will al- ways give the current user1/irq12 pin value, regard- less of pin configuration setting. in addition to the functionality listed above, the user1/irq12/extcts/exint188 pin may be used to enable the internal tx state machine. this capability is controlled by the ctsen bit of tcr7 and operates inde- pendently of the table above and independently of the u1intcnt bits of tcr7. when the ctsen bit of tcr7 is set to 1, then the value of the user1/irq12/ extcts/exint188 pin will be anded with the value of the txs bit of tir8. the output of the and gate will then be used to determine the start of the tx state machine. in this way, an external signal, through the user1/irq12/extcts/exint188 input, can be used to control the start of the tx state machine, provided that AM79C930 device firmware has enabled the operation by setting the txs bit of tir8. in addition to the functionality listed above, the user1/irq12/extcts/exint188 pin may be used to produce interrupts to the 80188 embedded controller. this capability is controlled by the u1intcnt bits of tcr7 and operates independently of the bits in the table above and independently of the ctsen bit of tcr7.interrupts that are routed through the user1/irq12/extcts/exint188 pin are indicated in the u1int bit of tcr11. the following table lists the pro- gramming options for using the user1/irq12/ extcts/exint188 pin as a source of external interrupt to the 80188 controller. u1intcnt user1 pin u1int bit tcr7[4:3] event result (tcr11[3]) 00 x 0 => interrupt disabled reset default condition 01 rising edge 1 => interrupt signalled 10 falling edge 1 => interrupt signalled 11 rising or falling edge 1 => interrupt signalled pin 92: user7/irq11 the user7/irq11 pin may be configured for input op- eration, output operation, or isa irq11 operation ac- cording to the following table: note that a read of the user7dl bit (tir29[7]) will al- ways give the current user7/irq11 pin value, regard- less of pin configuration setting. user7dl (tir29[7]) gives the current value of the user7/irq11 pin. user7/ user7/ pcmcia user7fn user7en irq select irq type irq11 irq11 pin tc30[7] tcr14[7] pnpx70 pnpx71 pin direction pin data 0 0 x bh 2h o irq11 0 0 x bh 1h od irq11 00 x 1 bh x i na 01 x x x i na 10 0 x x i na 1 0 1 x x o tir29[7] 11 x x x i na amd p r e l i m i n a r y 36 AM79C930 pin 94: rxc/irq10/exta2dst the rxc/irq10 pin may be configured for input opera- tion, output operation, isa irq10 operation, and as an output providing the rx clock information (whether de- rived from the rxdata stream through AM79C930 device dpll operation or simply rerouted from the rxcin input) according to the following table: note that a read of the rxcd bit (tir11[7]) will always give the current rxc/irq10 pin value, regardless of pin configuration setting. in addition to the functionality listed above, the rxc/ irq10/exta2dst pin may be used to control the start of the a/d conversion process. when the uxa2dst bit of tcr25 has been set to a 1, then the normal internal state machine control of the a/d sample and conversion procedure or a rising edge on the rxc/ irq10/exta2dst pin will trigger an a/d conversion procedure. by allowing external control of the start of the a/d conversion process, the extadtst input allows synchronization of the internal a/d function to an exter- nal circuit that desires to use the a/d converter. rxc/ rxc/ pcmcia rxcfn rxcen irq select irq type irq10 irq10 pin tcr28[7] tcr15[4] pnpx70 pnpx71 pin direction pin data 0 0 x ah 2h o irq10 0 0 x ah 1h od irq10 000 1 ah x i tir11[7] 001 1 ah x o tir11[7] 0 1xxxorxc 1 0 0 x x i tir11[7] 1 0 1 x x o tir11[7] 1 1xxxorxc pin 95: user6/irq5/extsdf the user6/irq5/extsdf pin may be configured for input operation, output operation, or isa irq5 operation according to the following table: note that a read of the user6d bit (tir11[6]) will al- ways give the current user6/irq5 pin value, regard- less of pin configuration setting. user6/ user6/ pcmcia enxsdf user6fn user6en irq select irq type irq5 irq5 pin tcr28[6] tcr7[6] tcr15[3] pnpx70 pnpx71 pin direction pin data 0 1 x x x x i tir11[6] 0 x 0 x 5h 2h o irq5 0 x 0 x 5h 1h od irq5 0000 1 5h x i tir11[6] 0001 1 5h x o tir11[6] 0 0 1 0 x x i tir11[6] 0 0 1 1 x x o tir11[6] 1 1 x x x x i tir11[6] 1 0 x 0 x x i tir11[6] 1 0 x 1 x x o tir11[6] in addition to the functionality listed above, the user6/irq5/extsdf pin may be used to enable the function of the rx state machine within the AM79C930 device. this capability is controlled by the enxsdf bit and the enxchbsy bit, both of tcr28. when the enxsdf bit and the enxchbsy bit of tcr28 are both set to a 1 and either tcr28 bit 4 is set to 0 or an antenna selection has been made, then the value of the user6/irq5/extsdf pin will be used to enable trans- fers of rxd data into the rx fifo, provided the AM79C930 device firmware has previously enabled the rx state machine by setting the rxs bit of tir16. in addition, the extsdf value will be sent to the sdf inter- rupt bit of tir5[2]. tir5[2] will, if unmasked, produce an interrupt to the 80188 embedded controller. note that setting the enxsdf bit of tcr28 to a 1 will cause the user6/irq5/extsdf pin to function as an input, regardless of other control bit settings. pin 96: user5/irq4/extchbsy the user5/irq4 pin may be configured for input op- eration, output operation, or isa irq4 operation accord- ing to the table below. note that a read of the user5d bit (tir11[5]) will al- ways give the current user5/irq4/extchbsy pin value, regardless of pin configuration setting. in addition to these bits, the user5/irq4/extchbsy pin may be used to produce interrupts to the 80188 embedded controller. this capability is controlled by the p r e l i m i n a r y amd 37 AM79C930 enxchbsy bit of tcr28 and the chbsyu bit of tir5 and operates independently of the bits in the table below. in addition to the functionality listed above, the user5/irq4/extchbsy pin may be used as the source for cca information, instead of relying on the in- ternal cca logic of the AM79C930 device. when using the external cca information, cca information from the internal logic will be unavailable. external cca informa- tion will appear in the same register bit locations as in- ternal cca information, when enabled, so a change from internal source to external source will be transpar- ent to firmware (excepting the necessary change in the enxchbsy bit value). this source of cca information is controlled by the enxchbsy bit of tcr28. when the enxchbsy bit of tcr28 is set to a 1, then the value of the user5/irq4/extchbsy pin will be fed directly to the chbsyc bit of tir4, chbsy bit of tir26 and the bcf bit of tir5. if the chbsyc interrupt is unmasked, it will produce an interrupt to the 80188 embedded controller. if the bcf interrupt is unmasked, it will produce an inter- rupt to the 80188 embedded controller. note that setting the enxchbsy bit of tcr28 to a 1 will cause the user5/irq4/extchbys pin to function as an input, regardless of the settings of the other control bits listed. user5/ user5/ pcmcia enxchbsy user5fn user5en irq select irq type irq4 irq4 pin tcr28[5] tcr7[5] tcr15[2] pnpx70 pnpx71 direction pin data 0 1 x x x x i tir11[5] 0 0 0 x 4h 2h o irq4 0 0 0 x 4h 1h od irq4 0000 1 4h x i tir11[5] 0001 1 4h x o tir11[5] 0 0 1 0 x x i tir11[5] 0 0 1 1 x x o tir11[5] 1 1 x x x x i tir11[5] 1 0 x 0 x x i tir11[5] 1 0 x 1 x x o tir11[5] pin 98: act the act pin may be configured for input or output op- eration. the output drive may be programmed for totem pole or open drain operation. act pin configuration is accomplished according to the following table: note that a read of the act bit (tir0[6]) will always give the current act pin value, regardless of pin configuration setting. acten act actdr act pin act pin tcr15[1] tir0[6] tcr27[3] direction value 0x x i na 1 0 0 od float reset default condition 1 1 0 od low 1 0 1 o high 1 1 1 o low pin 100: lnk the lnk pin may be configured for input or output op- eration. the output drive may be programmed for totem pole or open drain operation. lnk pin configuration is accomplished according to the following table: note that a read of the lnk bit (tir0[7]) will always give the current lnk pin value, regardless of pin configuration setting. lnken lnk lnkdr lnk pin lnk pin tcr13[7] tir0[7] tcr27[4] direction value 0x x i na 1 0 0 od float reset default condition 1 1 0 od low 1 0 1 o high 1 1 1 o low amd p r e l i m i n a r y 38 AM79C930 pin 101: sdclk the sdclk pin may be configured for input or output operation. the output drive may be programmed for reg- ister-driven or auto-pulse generation. the auto-pulse may be programmed for either active low or active high operation. sdclk pin configuration is accomplished ac- cording to the following table: note that a read of the sdc bit (tir2[2]) will always give the current sdclk pin value, regardless of pin configuration setting. sdclken sdcp sdc sdclk pin sdclk pin tcr13[4] tir2[3] tir2[2] direction value 0x x i na 1 0 0 o low reset default condition 1 1 0 o high active pulse (when write to tir2 occurs) 1 0 1 o high 1 1 1 o low active pulse (when write to tir2 occurs) pin 102: sddata the sddata pin may be configured for input or output operation. sddata pin configuration is accomplished according to the following table: note that a read of the sdd bit (tir2[0]) will always give the current sddata pin value, regardless of pin configuration setting. sddt sdd sddata pin sddata pin tir2[1] tir2[0] direction value 0 0 o low reset default condition 0 1 o high 1x i na pin 103: sdsel3 the sdsel [ 3 ] pin may be configured for input or output operation according to the following table: note that a read of the sds[3] bit (tir2[6]) will always give the current sdsel [ 3 ] pin value without inversion, regardless of pin configuration setting. sdsel3 en sds[ 3 ] sdsel [ 3 ] sdsel [ 3 ] tcr13[3] tir2[6] pin direction pin value 0x i na 1 0 o high reset default condition 1 1 o low pin 105: sdsel2 the sdsel [ 2 ] pin may be configured for input or output operation according to the following table: note that a read of the sds[2] bit (tir2[5]) will always give the current sdsel [ 2 ] pin value without inversion, regardless of pin configuration setting. sdsel2 en sds[ 2 ] sdsel [ 2 ] sdsel [ 2 ] tcr13[2] tir2[5] pin direction pin value 0x i na 1 0 o high reset default condition 1 1 o low pin 107: sdsel1 the sdsel [ 1 ] pin may be configured for input or output operation according to the following table: note that a read of the sds[1] bit (tir2[4]) will always give the current sdsel [ 1 ] pin value without inversion, regardless of pin configuration setting. sdsel1 en sds[1] sdsel [1] sdsel [1] tcr13[1] tir2[4] pin direction pin value 0x i na 1 0 o high reset default condition 1 1 o low p r e l i m i n a r y amd 39 AM79C930 pin 115: txc the txc pin may be configured for input or output op- eration according to the table below: txc input configuration is the reset default configura- tion. this configuration allows an external transceiver to control the clock that serves as the reference for the transmit data. while in this configuration, the internal tx state machine continues to operate with a reference clock derived from a divided version of the clkin input. since the external txc source is not driving the AM79C930 device tx state machine, there exists a synchronizing fifo between the crc generator and the txdata pin that is used only in the txc input mode. this serial fifo is 16 bits long and is used to allow for slight mismatch between the internal tx state machine reference clock and the external txc input clock. it is imperative in the txc input mode that the data rate se- lected with the data rate bits of tcr30 must match the expected txc clock rate from the transceiver. if these rates do not match, then there is a risk of internal serial fifo error which, if it occurred, would be signaled through the atfu and atfo interrupts of tcr11. txcin txc pin txc pin tcr30[3] direction value 0 o txc (result of internal divide of clkin) 1 i na reset default condition pin 118: lfpe the lfpe pin may be configured for input or output op- eration according to the table below: note that a read of the lfpe bit (tir0[1]) will always yield the inverted logical sense of the current lfpe pin value, regardless of pin configuration setting. note that the value of the lfpe bit (tir0[1]) also affects the value of the lfclk pin. lfpeen lfpe clkgt20 lfpe pin lfpe pin lfclk pin tcr13[6] tir0[1] mir9[7] direction value value 0 x x i na low 1 0 x o high low reset default condition 1 1 0 o low clkin 1 1 1 o low clkin ? 2 pin 120: hfpe the hfpe pin may be configured for input or output op- eration according to the following table: note that a read of the hfpe bit (tir0[0]) will always yield the inverted logical sense of the current hfpe pin value, regardless of pin configuration setting. note that the value of the hfpe bit (tir0[0]) also affects the value of the hfclk pin. hfpeen hfpe clkgt20 hfpe pin hfpe pin hfclk pin tcr13[5] tir0[0] mir9[7] direction value value 0 x x i na low 1 0 x o high low reset default condition 1 1 0 o low clkin 1 1 1 o low clkin ? 2 pin 122: rxpe the rxpe pin may be configured for input or output op- eration according to the following table: note that a read of the rxp bit (tir0[2]) will always yield the inverted logical sense of the current rxpe pin value, regardless of pin configuration setting. rxpelen rxp rxpe pin rxpe pin tcr13[0] tir0[2] direction value 0x i na 1 0 o high reset default condition 1 1 o low amd p r e l i m i n a r y 40 AM79C930 pin 126: txcmd the txcmd pin may be configured to drive a trans- ceiver control reference signal, using one of two timing sources plus input from the txcmd bit of tir11 (tir11[0]), according to the following table: rcen txcmd pin txcmd pin tir11[3] direction value 0 o o_tx 1o tir11 [ 0 ] & t1 transmit state machine generated signals t1 , t2 , t3 , txp _ on and o_tx have the timing indicated in the diagram in section AM79C930-based tx power ramp control. pin 129: txpe the txpe pin may be configured to drive a transceiver control reference signal, using one of two timing sources plus input from the txpe bit of tir11 (tir11[1]) and the txpepol bit of tcr27, according to the following table: transmit state machine generated signals t1 , t2 , t3 , txp _ on and o_tx have the timing indicated in the diagram in section AM79C930-based tx power ramp control. rcen txpepol txpe pin txpe pin tir11[3] tcr27[1] direction value 0 0 o txp_on 0 1 o txp_on 10o tir11 [ 1 ] & t2 (& = logical `and') 1 1 o tir11[1] + t2 (+ = logical `or') pin 131: txmod the txmod pin may be configured to drive a trans- ceiver control reference signal, using input from the txmod bit of tir11 (tir11[2]) and the txmodpol bit of tcr27, according to the following table: transmit state machine generated signals t1 , t2 , t3 , txp _ on and o_tx have the timing indicated in the diagram in section AM79C930-based tx power ramp control. rcen txmodpol txmod pin txmod pin tir11[3] tcr27[0] direction value 00o t3 01o t3 10o tir11 [ 2 ] & t3 (& = logical `and') 1 1 o tir11[2] + t3 (+ = logical `or') pin 132: antslt the antslt pin may be configured to drive an inter- nally generated antenna selection signal using the inter- nal antenna diversity circuitry, or it may be controlled by a register bit. pin functionality is programmed according to the following table: if it is necessary to force antslt to be always constant, then program ants to 0 or user antslt pin, which can be controlled by antsltd (tcr7:[1]). tx antsen anten mode (tir16[[3]) (tir4:[7]) 0 0 0 antslt <= low 0 1 0 antsel <= ants (tir26:[4]) 0 x 1 antslt <= internal antsel 1 x x antslt <= low pin 141: antslt /la23 the antslt /la23 pin may be configured to operate as input or output and may be configured to drive an internally generated antenna selection reference signal using the internal antenna diversity circuitry. note that p r e l i m i n a r y amd 41 AM79C930 some functionality is only available in pcmcia mode. pin functionality is programmed according to the follow- ing table: note that a read of the antsltd bit (tcr7[1]) will al- ways give the current antslt /la23 pin value without inversion, regardless of pin configuration setting. antslt / antslt / pcmcia antsen ansltlfn antsltlen la23 pin la23 pin pin value tir26[3] tcr30[7] tcr15[7] direction value 0 x x x i na (la23 input function) 100xo antslt (from internal antenna) (diversity circuit) 1x10i na 1 x 1 1 o tcr7[1] 110xo tir26 [ 4 ] (write) tir26 [ 5 ] (read) pin 142: txcmd/la21 the txcmd/la21 pin may be configured to operate as input or output and may be configured to drive a trans- ceiver control reference signal using one of two timing sources plus input from the txcmd bit of tir11 (tir11[0]). note that some functionality is only available in pcmcia mode. pin functionality is programmed according to the following table. transmit state machine generated signals t1 , t2 , t3 , txp _ on and o_tx have the timing indicated in the diagram in section AM79C930-based tx power ramp control. note that a read of the txcmdt bit (tcr7[2]) will al- ways give the current txcmd/la21 pin value without inversion, regardless of pin configuration setting. txcmd/ txcmd/ pcmcia rcen txcmfn txcmen la21 pin la21 pin pin value tir11[3] tcr30[5] tcr15[5] direction value 0 x x x i na (la21 input function) 1 0 x x o o_tx 1 1 0 x o tir11[0] + t1 1110i na 1 1 1 1 o tcr7[2] pin 143: txdata /la20 the txdata /la20 pin may be configured to operate as input or output and may be configured to drive inverted transmit data. note that some functionality is only available in pcmcia mode. pin functionality is pro- grammed according to the following table: the txdata signal is the inverse of the txdata signal which is the tx data drawn from the tx fifo using the internal tx state machine control. note that a read of the txdatald bit (tcr7[0]) will al- ways give the current txdata /la20 pin value without inversion, regardless of pin configuration setting. txdata / txdata / pcmcia txdlfn txdlen la20 pin la20 pin pin value tcr30[6] tcr15[6] direction value 0 x x i na (la20 input function) 10xo txdata (from internal tx fifo using internal tx state machine timing) 110ina 1 1 1 o tcr7[0] pin 144: llocke/sa15 the llocke/sa15 pin may be configured to operate as input or output. note that some functionality is only avail- able in pcmcia mode. pin functionality is programmed according to the following table: note that a read of the llocke bit (tir11[4]) will al- ways give the current llocke/sa15 pin value without inversion, regardless of pin configuration setting. amd p r e l i m i n a r y 42 AM79C930 llocke/ llocke/ pcmcia llocken sa15 pin sa15 pin pin value tcr14[6] direction value 0 x i na (sa15 input function) 10 i na 1 1 o tir11[4] functional description basic functions system bus interface function the AM79C930 device is designed with a choice of two system bus interfaces. the system designer may choose between the pcmcia bus and the isa (ieee p996) bus with support for plug and play. both inter- faces support an 8-bit wide data bus. the system inter- face is used by the host driver software to initialize the AM79C930 device through a series of slave i/o ac- cesses to the AM79C930 device. device operation is monitored by accessing AM79C930 registers through the system bus interface. network data is transferred to/from the driver through slave memory accesses at the system bus interface. network data is stored in the sram that accompanies a complete AM79C930- based design. memory bus interface function the AM79C930 device contains a memory bus inter- face, which is used by the AM79C930 device to gain ac- cess to flash memory for fetching 80188 instructions and to gain access to sram for fetching and storing driver commands, network data, and for temporary vari- able storage. software driver transfers of network data are passed to the AM79C930 device through the system bus interface and will be automatically rerouted to the memory bus interface in order to reach the sram. software interface function the software interface to the AM79C930 consists of a set of 256k memory locations and 16 (or 40) i/o loca- tions. 128k of these memory locations map directly to an sram that is attached to the memory interface. an- other 128k maps to a flash memory device. due to overlapping address space as viewed by the 80188 embedded processor core, 128 bytes of the sram space are not usable for driver function. additional registers exist in the AM79C930 device for use by industry standard pcmcia and isa plug and play configuration utilities. network interface function the AM79C930 device can be connected to an ieee 802.11 (draft) network via a flexible network interface. the flexible network interface allows the user to define much of the pin functionality in order to assist in accom- modating the AM79C930 device to a number of different network transceivers. pin control is achieved through transceiver attachment interface (tai) registers (tir and tcr). these registers are controlled through 80188 firmware instructions. detailed functions block level description bus interface unit the bus interface unit (biu) supports either of two com- mon interfaces: pcmcia and isa (ieee p996) with plug and play. the choice of interface is determined through a pin strapping option via the pcmcia pin. two sets of command and status registers exist within the biu. one set of registers is labeled system interface registers (sir). the sir registers are used to control the general function of the device by providing various resets and by allowing some direct communication be- tween the host system and the embedded 80188. the sir registers are visible to the system interface, but are not visible to the 80188 embedded core. the second set of biu registers is the mac interface registers (mir). the mir registers are visible to the 80188 embedded core, but are not visible from the system interface. some commands within each register set allow indirect communication between the system interface and the 80188 core. another set of registers is located in the transceiver at- tachment interface unit, the tir registers. the tir loca- tions are visible through the biu. these registers are normally used by the 80188 core to control the trans- ceiver function; they are visible through the system interface primarily for diagnostic purposes. the pcmcia card configuration registers and the set of isa plug and play registers are implemented in the biu. pcmcia card information structure and the isa plug and play resource data area are both mapped to flash space and are accessible through the system interface of the biu. all AM79C930 registers are located in i/o space as viewed from the system interface. there are no memory resources located inside of the biu unit, although there are memory resources that are accessed through the biu. for a complete description of all resources accessible inside of and through the biu, see the soft- ware access section. for a complete description of all resources accessible by the embedded 80188 processor, see the 80188 firmware section. p r e l i m i n a r y amd 43 AM79C930 pcmcia interface the AM79C930 device fully sup- ports the pcmcia standard, revision 2.1. the pcmcia interface on the AM79C930 device sup- ports both memory and i/o cycles. the data bus is 8 bits in width. the address bus is 15 bits in width. memory ac- cesses are enabled by default at power up. i/o ac- cesses are enabled only when the confindex bits of the pcmcia configuration option register have a non-zero value. it is not possible to disable the memory access response function. the AM79C930 device re- quires 32k of common memory space and 16 or 40 bytes of i/o space. since all AM79C930-based memory resources are also mapped into an i/o port, it is possible to operate with a common memory space allo- cation of 0 bytes. the AM79C930 device supports the card information structure and the card configuration registers defined in the pcmcia 2.1 standard, by decoding 2k+4 bytes of attribute memory space. the first tuple of the card infor- mation structure must be located at pcmcia attribute memory location 0h. note that in the AM79C930 device, attribute memory locations 000hC07ffh are mapped to the upper 1 kbytes of the 128k flash memory space (i.e., flash memory locations 1fc00hC1ffffh). the upper 1kC16 byte locations of the flash memory device must be reserved for pcmcia card information struc- ture use. (the uppermost 16 bytes of the flash memory may not be used for pcmcia cis space, since the 80188 core will fetch its first instructions from these lo- cations following a reset operation. these locations cor- respond to pcmcia attribute memory locations 7f0hC7ffh.) note that the 2 kbytes of attribute memory 0000hC07ffh are mapped to only 1 kbytes of flash memory. since the pcmcia specification indicates that only even addressed bytes of attribute memory are de- fined to exist, only the even addressed 1k of the 2k at- tribute memory space is actually physically present. odd addressed attribute memory locations in the AM79C930 device are undefined. while the common memory space of the AM79C930 device only accommodates access to 32 kbytes of common memory, the AM79C930 device uses device select and bank select bits (bits 5:3 of the bss register (sir1)) in order to access a total of 256k of memory space. when accessing common memory resources through pcmcia common memory accesses, lower memory addresses at the pcmcia interface are passed directly to the memory interface bus, and the flash memory chip enable ( fce ) or the sram chip enable ( sce ) sig- nal is asserted, depending upon the value of sir1[5]. the upper two bits of the memory interface address bus are set according to the value of sir1[4:3]. the pcmcia memory access control signals ( we , oe , ce1 ) are automatically translated into the appropriate memory interface signals ( rd , wr ). the pcmcia card configuration registers that are sup- ported are the configuration option register and the card configuration and status register. these two reg- isters are physically located in the bus interface unit and logically exist only in pcmcia attribute memory space (i.e., they are not also mapped to common memory space.) they are located at attribute memory locations 0800h and 0802h, respectively. the location of these registers is fixed. therefore, the information programmed into the cis must give the value 2k (=0800h) as the card configuration registers base address in the tpcc_radr field of the configuration tuple. the pcmcia card configuration registers are the only writable pcmcia attribute memory locations within the AM79C930, because these two registers do not corre- spond to flash memory locations, and these two loca- tions are not cis structures. the AM79C930 device occupies either 16 bytes of i/o space or 40 bytes of i/o space, depending upon the set- ting of the eiow bit (bit 2 of the bss register (sir1)). the i/o space of the AM79C930 contains the general configuration register, the bank switching select register, and the set of 32 tir registers. additionally, all AM79C930 resources are accessible through i/o ac- cesses (i.e., all memory structures are accessible through the local memory address and i/o data ports). the local memory address port (sir2,3) plus sir1[5:3] function together as a pointer to the memory resources of the AM79C930 device. sir1[5] determines the de- vice selected (sram or flash) and sir1[4:3] and lma[14:0] supply the address to the selected device whenever the i/o data port is read or written. whenever any of the four i/o data ports is accessed, then the lo- cal memory address port value is automatically incre- mented by a value of 1. because of the existence of the local memory address and i/o data ports, the AM79C930 device may be used in an i/o only fashion. appropriate configuration information may be placed into the cis space so that the pcmcia configuration utility will assign no memory space to the AM79C930-based design. note, however, that the AM79C930 device will always respond to com- mon memory accesses that are directed to the 0000hC7fffh range, if they occur in the pcmcia slot in which the AM79C930-based design resides. the common memory slave response function is always ac- tive on the AM79C930 device; it is not possible to dis- able this function. the AM79C930 device does not attempt to interpret the confindex value of the pcmcia configuration option register except for purposes of enabling the i/o slave response function. amd p r e l i m i n a r y 44 AM79C930 isa (ieee p996) plug and play interface the AM79C930 device fully supports the isa plug and play specification, revision 1.0a. the isa plug and play interface on the AM79C930 de- vice supports both memory and i/o cycles. the data bus is 8 bits in width. the total system space required by the AM79C930 device is 32 kbytes and 16 bytes of i/o space. since all AM79C930-based memory resources are also mapped into an i/o port, it is possible to operate a AM79C930-based design with a system memory allo- cation of 0 bytes. when the 32k system memory option is selected, the AM79C930 device uses device select and bank select bits in the bss register (sir1) in order to allow system access to a total of 256k of AM79C930 memory re- sources. the total system i/o space required by the AM79C930 device is 16 bytes. the 40-byte i/o option is not available in the isa plug and play mode of opera- tion. the eiow bit (bit 2 of the bss register (sir1)) will be forced to 0 when the AM79C930 device has been placed into isa plug and play mode. the i/o space of the AM79C930 device contains the general configura- tion register, the bank switching select register, and the set of 32 tir registers. additionally, all AM79C930 resources are accessible through i/o accesses (i.e., all memory structures are accessible through the local memory address and data ports (sir2,3,4,5,6,7)). the local memory address port plus sir1[5:3] function together as a pointer to the memory resources of the AM79C930 device. sir1[5] determines the device se- lected (sram or flash) and sir1[4:3] and lma[14:0] supply the address to the selected device whenever the i/o data port is read or written. whenever any of the four i/o data ports is accessed, then the local memory address port value is automatically incremented by a value of 1. the AM79C930 device maps 1kC16 bytes of the upper 1k of the 128k of flash memory space into the isa plug and play resource data structure. (the upper 16 bytes of this space may not be used for isa plug and play re- source data, since this space is needed to store the first instructions that will be fetched by the 80188 core follow- ing the reset operation.) byte 0 of the AM79C930 de- vice's resource data is mapped to location 1fc00h of the flash memory. reads of the isa plug and play data resource register will automatically access flash mem- ory locations in the range 1fc00h through 1fff0h. since all flash memory locations are always accessible through ordinary isa memory accesses, isa memory accesses to locations mba+7c00h C mba+7ff0h will sometimes correspond to the same physical locations as isa plug and play accesses to resource data bytes 000h C 3f0h (i.e., the correspondence will occur when the device and bank select bits of sir1 are pointing at the upper quadrant of the 128k flash memory address space). when accessing AM79C930 memory resources through isa memory cycle accesses, the upper 9 bits of the isa memory address will be used to check for a match of the address range assigned to the AM79C930 device by the plug and play configuration program (i.e., the memory base address = mba). (the plug and play configuration program will have written a memory base address value into the memory base address regis- tersplug and play ports 40h and 41hfollowing sys- tem boot up and auto-configuration.) the isa plug and play memory base address must be aligned to a 32k boundary in memory space. this alignment requirement should be included in the resource data that is pro- grammed into the flash device and read by the plug and play configuration utility. these conditions must be sat- isfied, since the AM79C930 device's bus interface unit will use the upper 9 bits of the isa memory address to determine when an address match has been achieved. when accessing AM79C930 memory resources through isa system memory accesses and when the upper bits of the isa address are determined to match the AM79C930 memory space, then the lower memory addresses at the isa interface are passed directly to the memory interface bus, and the flash memory chip en- able ( fce ) or the sram chip enable ( sce ) signal is as- serted, depending upon the value of sir1[5]. the upper two bits of the memory interface bus are set according to the value of sir1[4:3]. isa memory access control sig- nals ( memr , memw ) are automatically translated into the appropriate memory interface signals ( rd , wr ). when accessing AM79C930 i/o resources through isa i/o cycle accesses, the upper 8 bits of the isa system address will be ignored. only the lower 16 bits of ad- dress will be used to check for a match of the address range assigned to the AM79C930 device by the plug and play configuration program (i.e., the i/o base ad- dress = ioba). (the plug and play configuration pro- gram will have written an i/o base address value into the i/o base address registersplug and play ports 60h and 61hfollowing system boot up and auto-configura- tion.) the isa plug and play i/o base address must be aligned to a 16-byte boundary in i/o space. this align- ment requirement should be included in the resource data i/o port descriptor base alignment field that is programmed into the flash device and read by the plug and play configuration utility. these conditions must be satisfied for proper operation. the AM79C930 device fully supports the plug and play auto-configuration scheme. the plug and play address port, write_data port and read_data port are all supported, as well as 19 of the isa plug and play registers. for more detail, see the isa plug and play section. p r e l i m i n a r y amd 45 AM79C930 memory interface the memory interface is provided to support direct con- nection of both a non-volatile memory (typically flash memory) and an sram and an additional peripheral de- vice. separate chip enables for flash, sram, and an extra peripheral device exist in the memory interface. the 32k range of address space visible at the system interface (either pcmcia or isa plug and play) maps to a total of 256k of memory through the use of a device select bit and bank switching bits in the bank switching select register (sir1). 128k of space is reserved for flash memory and 128k of space is reserved for sram. the 32 bytes of space reserved for the extra pe- ripheral device are only accessible by the embedded 80188 core. the internal transceiver attachment unit also resides on the memory interface bus and uses 8 bytes (or 32) bytes of i/o space as viewed by the system interface. these same registers occupy 32 bytes of the sram's memory space (i.e., instead of i/o space) as viewed by the embedded 80188 core. the mir registers of the biu occupy an additional 16 bytes of sram space as viewed by the embedded 80188 core. the mir registers are not visible to the system interface. the memory interface bus is shared between the sys- tem interface and the embedded 80188 processor. memory interface bus sharing between the system in- terface and the 80188 processor core is based upon an equal priority delivered in a round robin fashion. when- ever the system interface is accessing a device on the memory interface bus, then the 80188 core is placed into ready wait. whenever the 80188 core is accessing a device on the memory interface bus, then the system in- terface bus activity will be given a ready wait. when the current memory interface bus master has completed its cycle, then the other memory interface bus master will be given control of the memory interface bus. the 80188 memory accesses are directed toward flash, sram, the xce peripheral device, tai registers (tir/tcr), or biu registers (mir) according to the ucs and lcs signals of the 80188 core. normally, whenever ucs is active during an 80188 memory access, the ac- cess is directed toward the flash memory; and when- ever lcs is active during an 80188 memory access, the access is directed toward the sram memory or the xce peripheral device or the tai registers or biu regis- ters. along with the ucs and lcs signals, 17 of the 80188 address lines are internally connected through the biu to the memory interface bus, allowing 256k of memory to be addressed by the 80188. (128k of flash and 128k of sram/ xce /tai/biu may be addressed by the 80188, for a total of 256k of memory.) an alternate addressing mode will alias the upper 96 kbytes of flash memory into the upper 96 kbytes of sram space, while preserving the location of the lower 32k of sram, the xce peripheral, and the tai/biu registers. this mode allows for 32k of sram/ xce /tai/ biu and 32k of flash to reside in a single 64 kbyte seg- ment of 80188 memory space. this mode is selected through a bit in the mir0 register. the tai connects to only a portion of the memory inter- face bus. specifically, the lowest five address bits and the entire data bus of the memory interface connect to the tai. a separate internal chip select signal for the tai exists to avoid confusion among slave devices. this sig- nal is not available on the AM79C930 memory interface bus, and therefore, memory interface cycles may be ob- served for which neither the flash chip enable, nor the sram chip enable, nor the xce signal is asserted. similar behavior is observed when the 80188 core is ac- cessing registers which are located within the biu. embedded 80188 the embedded 80188 core provides the basic means for implementing ieee 802.11 (draft) mac functionality. the elements of the AM79C930 device that are involved in mac function include the 80188 core, the flash mem- ory, the sram memory, the timers within the 80188, the sleep timer in the biu, the transceiver attachment unit, and the associated busses and signaling that connect the 80188 core to the biu and the transceiver attachment unit. the AM79C930 device directly incorporates some of the basic protocol requirements for operation of a ieee 802.11 (draft) node. other portions of the ieee 802.11 (draft) mac protocol need to be created with appropri- ate firmware written to execute on the 80188 core. with proper 80188 coding, the AM79C930 device can be made to operate according to the ieee 802.11 (draft). media access management the ieee 802.11 (draft) protocol defines a media access mechanism which permits all stations to access the channel with equality. synchronous time-bounded service and asyn- chronous time-bounded access service are also defined in the ieee 802.11 (draft) specification. any node can attempt to contend for the channel by waiting for a pre- determined time (inter frame spacing) after the last ac- tivity, and then waiting an additional random backoff time before determining whether to attempt to transmit on the media. if two or more nodes simultaneously con- tend for the channel, their signals will interact causing loss of data, defined as a collision. it is the responsibility of the mac to attempt to avoid and recover from a colli- sion in order to insure data integrity for the end-to-end transmission to the receiving station. medium allocation the ieee 802.11 (draft) standard requires that each carrier sense multiple access/collision avoidance (csma/ca) mac monitor the medium for traffic by watching for carrier activity. when carrier is detected, amd p r e l i m i n a r y 46 AM79C930 the media is considered busy and the mac should defer to the existing message. this function is implemented in hardware in the tai unit. additionally, each station is required to implement a net allocation vector (nav) in order to determine when the medium is expected to be busy. the nav is updated as request-to-send (rts), send (cts), and data frames arrive at the station. rts, cts, and data frames include a field that indicates the expected length of the rts-cts-data-ack exchange. the mac uses the value in this field to update the nav and then defers from initiating transmissions until the nav has counted down to zero. if any portion of the rts-cts-data-ack exchange is missing, then a mac timer will timeout and the nav is reset to zero at that time. by refraining from transmission while the nav is non-zero, the mac is practicing collision avoidance. nav values may be maintained through use of one of the 80188 timers. if there is no backoff in progress when the nav counter value times out, the firmware will initi- ate transmission of a frame. initialization AM79C930 device initialization is per- formed by asserting the AM79C930 reset input for more than 14 clocks. following the release of the reset signal, the AM79C930 device's embedded 80188 core will exit the reset state. the embedded 80188 will then proceed with instruction fetching and execution from memory location ffff0h. the first fetch will occur within 13 clkin clocks (= 6 and 1/2 80188 cpu clock cycles) of the release of the 80188 reset. the 80188 address ffff0h will map to a flash memory lo- cation, since the umcs register of the 80188 core will be set to fff8h following reset. this umcs value will en- sure that the initial 80188 address fetch will cause an as- sertion of the ucs signal, which will cause the memory interface bus logic to select the flash memory device. 80188 firmware must modify the value of the umcs reg- ister after the first few execution cycles in order to make more than 1k of the flash memory available to the 80188 core. the 80188 firmware should make no access to mir reg- isters or to tai registers (tir and tcr) until the follow- ing steps have been completed. note that these steps must be performed in the order given : 1. the 80188 firmware must perform a write to the 80188 internal lmcs register and set the wait states to 0 and set the ready control to also use external rdy (i.e., set r2,r1,r0 to 000b). no other value should be written to these bits. note that the value that will eventually be written to the biu mir8 register will cause the AM79C930 internal srdy signal to be asserted for the proper number of cycles and will cause the 80188 to experience the proper delay for the sram memory device in the AM79C930-based system. 2. the 80188 firmware must perform a write to the 80188 internal umcs register and set the wait states to 0 and set the ready control to also use external rdy (i.e., set r2,r1,r0 to 000b). no other value should be written to these bits. note that the value that will eventually be written to the biu mir9 register will cause the AM79C930 internal srdy signal to be asserted for the proper number of cycles and will cause the 80188 to experience the proper delay for the flash memory device in the AM79C930-based system. 3. the 80188 firmware must perform a write to the AM79C930 internal mir8 register and set the flash- wait bits to a value that is appropriate for the flash memory timing, given the AM79C930 clkin pin fre- quency and the particular speed-grade of the flash memory used in the design. 4. the 80188 firmware must perform a write to the AM79C930 internal mir9 register and set the sramwait bits to a value that is appropriate for the sram memory timing, given the AM79C930 clkin pin frequency and the particular speed-grade of the sram memory used in the design. sram memory management the 80188 core accesses the sram memory by asserting its lower chip select (80188 lcs ). (actually, sram space is se- lected whenever the 80188 memory access does not activate the ucs signal. the internal upper chip select ( ucs ) signal is routed into the bus interface unit, since the 80188 core and the bus interface unit must share the memory interface bus. when ucs is not activated for an 80188 transfer, the biu unit assumes that sram accesses are desired. therefore, during 80188 ac- cesses for which ucs is not asserted, sce will be as- serted, except for a section of lower memory space that is redirected toward the tai section of the AM79C930 device.) the sce signal may be attached to the ce in- put of an sram memory device external to the AM79C930 device. up to 128k of sram may be ad- dressed by the 80188 core (with the exception that 64 bytes of sram space is mapped into internal AM79C930 registers of the biu and tai.) an alternative mapping scheme allows some portion of the flash memory to be mapped into a portion of lcs space. (normally, flash memory is mapped only to ucs space.) therefore, depending upon the mapping scheme that is chosen, lcs may either access sram plus biu plus tai space, or lcs may access a portion of sram plus biu plus tai space plus a portion of flash memory space. for mapping details, see the section on mac firmware resources. address values are delivered from the 80188 core to the sram through the biu and then to the memory address bus (signals ma[16:0]). ad [7:0] 80188 address signals are latched inside of the biu to allow system interface p r e l i m i n a r y amd 47 AM79C930 accesses to use the memory interface bus during the t1 and t2 cycles of the 80188 access. the memory ad- dress bus is internally shared between the 80188 core and the biu. this bus also attaches to the transceiver attachment unit as an input only. data values are delivered from the 80188 core to the sram through the biu and then to the memory data bus (signals md[7:0]). this bus is shared by the biu for access to the sram and also attaches to the trans- ceiver attachment unit. flash memory management the 80188 core accesses the flash memory by assert- ing its upper chip select (80188 ucs ) this signal remains internal to the AM79C930 device. the internal ucs signal is routed into the biu, since the 80188 core and the biu must share the memory interface bus. the biu in turn produces the memory interface signal fce that may be attached to the ce input of a flash memory device external to the AM79C930 device. an alternative mapping scheme allows some portion of the flash memory to be mapped into a portion of lcs space. (normally, flash memory is mapped only to ucs space.) therefore, depending upon the mapping scheme that is chosen, flash memory may be visible only in ucs space, or portions of flash memory may be visible in both lcs and ucs spaces. for mapping details, see the section on mac firmware resources . address values are delivered from the 80188 core to the flash memory through the biu and then to the memory address bus (signals ma[16:0]). the memory address bus is shared between the 80188 core and the biu. the sharing uses a priority scheme where the requester al- ways has higher priority than the current bus master. this ensures that in the worst case the system interface access will be delayed only by the length of a single 80188 access, and an 80188 access will be delayed at most by the length of a single system interface access. the requesting access is always held off by asserting the local ready signal. the memory interface bus also attaches to the tai unit. the tai is a bus slave device; it cannot act as a bus master. data values are delivered from the 80188 core to the flash memory through the biu and then to the memory data bus (signals md[7:0]). up to 128k of flash mem- ory may be addressed by the 80188 core. note that for pcmcia operation, the 1kC16 bytes of the upper 1k locations may be used for the pcmcia cis, since these locations are mapped to attribute memory space when the pcmcia mode of operation has been selected. note that the uppermost 16 bytes of flash space are used by the 80188 core to fetch initial instructions following a reset operation of the AM79C930 device. therefore, these 16 bytes cannot be used for pcmcia cis. note that both the 80188 core and the system interface (through common memory mapping) have access to the pcmcia cis storage area, even though these loca- tions should be reserved for pcmcia cis use. transceiver attachment interface unit management the 80188 core communicates with the tai unit through memory accesses that the 80188 core performs on the memory interface bus through the biu. tir regis- ters are mapped to 32 byte locations of the sram space, thereby rendering those 32 bytes of sram as inaccessible to the 80188 core. command and status information for the tai is passed through the tir regis- ters. network data is passed to/from the tai fifos with dma cycles. the tai uses dma channels 0 and 1 of the 80188 core. dma channel 0 is used by the rx fifo and dma channel 1 is used by the tx fifo. the 80188 core must activate its lcs signal to access the tir registers, just as in the case of sram accesses. as a result, the tai register set overlaps a very small portion of the sram space. the tai may send interrupts to the 80188 core through the int0 interrupt. bus interface unit interaction the 80188 core communicates with the driver software through a shared area of sram. when either the driver software or the 80188 core modifies this area of sram, an interrupt is generated to notify the receiving subunit. most command and status information for the adapter may be passed to the driver through the shared sram. however, a few physical registers do exist in the biu to facilitate the exchange of some very high level com- mands, such as reset, halt, powerdown and interrupt. each subunit (device driver and 80188 core) is allotted its own set of biu registers. the device driver has access to eight system interface registers (sir) that reside in the biu. the 80188 core has access to 16 mac interface registers (mir) that reside in the biu. communication of high-level command and status information between the two subunits is indirectly accomplished, in that modification of bits in the sir space will affect bits in the mir space and vice versa, but the device driver has no direct access to the mir space and the 80188 core has no direct access to the sir space. amd p r e l i m i n a r y 48 AM79C930 transceiver attachment interface unit the tai unit includes the following subfunctions: tai register set tx fifo tx data serialization tx crc32 generation tx crc8 generation tx status reporting rx preamble and start of frame detection rx data deserialization rx fifo rx crc32 checking rx crc8 checking rx status reporting bit ordering rssi a/d circuit physical header accommodation encryption/decryption support data scrambling dc bias control baud determination logic cca circuit antenna diversity logic the tai provides the necessary functionality to directly connect to a variety of possible transceiver interface styles. in the pcmcia mode of operation, 24 pins are di- rectly controllable through register access by the device driver and the 80188 core firmware. these 24 pins may be combined with the fixed function pins of the network interface to create a customer-specific network inter- face. in the isa plug and play mode of operation, the number of programmable pins is reduced to 10, while the fixed function pins remain unchanged. the tai is logically located on the AM79C930 memory interface bus as a slave-only device. the tai contains 64 registers that are used to configure operational pa- rameters, to communicate commands, to pass data, and to pass status. thirty-two of the registers are di- rectly accessible to the 80188 core and to the system interface. these 32 registers are labeled tai interface registers (tir). an additional 32 tai registers are indi- rectly accessible through an address and data port in the tir register set. these 32 registers are labeled tai configuration registers (tcr). data transfers from the rx fifo are requested through the internal 80188 core input drq0. data transfers to the tx fifo are requested through the internal 80188 core input drq1. interrupts from the tai are requested through the internal 80188 core input int0. the tai supplies an antenna select pin to allow for se- lection between two possible antennas. the AM79C930 device has provision for both automatic and manual selection of antennas. if automatic antenna selection is not used, then the desired antenna selection is accom- plished through the setting of appropriate bits in one of the tir registers. tx fifo the tai contains individual fifos for rx and tx opera- tions. the tx fifo holds a maximum of 8 bytes. the tx fifo indicates a not full state by signaling a request for data on the drq1 input of the 80188 embedded core. the drq1 output of the tai subunit is active if the tx fifo condition is met, regardless of the state of the txs bit of tir8. tx fifo dma activity is prevented by dis- abling the dma1 controller in the 80188. the tx fifo holds a maximum of 8 bytes of data. actual tx fifo byte count can be read from tir9. preamble and start of frame delimiter and any necessary phy subunit header information must be assembled by the 80188 core firmware and then loaded into the tx fifo for inclusion in the tx frame. the tai subunit has no built in capabilities for preamble, sfd, or phy header generation. tx power ramp control the AM79C930 device includes state-controlled output signals that may be used to perform transceiver power sequencing. for transceivers that create their own transmit power sequencing, a single input signal (cts) is provided to allow for smooth synchronization between the AM79C930 device and the transceiver. AM79C930-based tx power ramp control the following is the description of the AM79C930 device's state-controlled output signals. the subsequent section is a description of the cts input signal and its intended use. once the tx start command has been issued to the tai by the 80188 core firmware (txs bit of tir8), a sequence of transceiver enable signals will be gener- ated in order to ramp up the power to the various sec- tions of the transceiver (i.e., txcmd , txpe , txmod ). once the final enable signal has been sent to the trans- ceiver, the tai will begin to remove data from the tx fifo. as each byte of data is removed from the tx fifo, the tai subunit will serialize the byte and send the individual bits of the data out the txdata pin at the specified data transmission rate. timing for the transmit ramp up and ramp down se- quence is generated from 5 internal signals whose tim- ing relationships may be directly controlled by register programming (tcr5, tcr6). the following diagram il- lustrates the relationships among the five internal sig- nals and the registers that control them. p r e l i m i n a r y amd 49 AM79C930 t1 txdata t2 t3 2 x tsclk tgap2 x tbclk + 2 x tsclk tgap1 x tbclk + 2 x tsclk 1st data bit last data bit 2 x tsclk txs 4 x tsclk tsclk = tclkin when clkgt20 = 0 tbclk = tsclk x 20 tgap3 x tbclk + 2 x tsclk o_tx txp_on 3 x tsclk hdb x tbclk tx default bit drb x tbclk tgap4 x tbclk + 2 x tsclk tx default bit 7 x tsclk 20183b-7 figure 1. transmitter power ramp control the values hdr, drb, tgap1, tgap2, tgap3, and tgap4 are programmable values that are stored in tcr register locations tcr0, tcr5, and tcr6. all other timings in the diagram are fixed with the values in- dicated. the clkgt20 control bit is located in mir9[7]. the timing of the five internal signals can be applied to the external pins txcmd , txpe , and txmod in either of two ways, depending upon the value pro- grammed into the rcen bit of tir11 as shown in the following table: pin timing reference timing reference name when rcen=0 when rcen=1 txcmd o_tx t1 txpe txp_on t2 txmod t3 t3 note that the txcmd, txpe, and txmod bits of tir11 may also affect the values of the txcmd , txpe , and txmod pins. see the individual descriptions of these pins in the multi-function pin section of this document for more detail. the polarity of txmod and txpe are programmable. a separate txcmd signal (inverse polarity to txcmd ) is available. amd p r e l i m i n a r y 50 AM79C930 transceiver based tx power ramp control the cts signal may be used to synchronize operations be- tween the AM79C930 device and transceivers that wish to perform their own transmit timing sequence. when the cts signal is enabled by setting the ctsen bit of tcr7 to a 1, then the cts input acts as a gating signal with respect to the start of the AM79C930 transmit op- erations. an example of the use of the cts signal would be when a transceiver is in control of the decision to transmit. the AM79C930 device must first indicate a de- sire to transmit by asserting one of the user-definable output pins to the transceiver and then by setting the txs bit of tir8. these actions place the AM79C930 de- vice's transmit state machine in a wait for cts state. when the transceiver concludes that the medium is free and a transmission may begin, then it asserts the cts signal to the AM79C930 device and the internal transmit state machine will begin to send data to the transceiver. for this application, the txcmd signal would indicate to the transceiver a desire to transmit, and the multifunction pin user1/irq12/extcts/ int188 would provide the return path to the AM79C930 device indicating the transceiver's decision to proceed with the transmission. tx crc generation a crc may be automatically calculated for each frame that is transmitted. the crc is automatically appended to the end of the frame when an appropriate tir bit has been set. the crc appended to the transmit frame de- pends upon the setting of the tcrc bits of tir8. either an 8-bit crc or a 32-bit crc may be appended. an op- tion to append no crc may also be selected. the crc that is selected may be changed on a per-frame basis. when the crc is appended to an outgoing frame, an in- terrupt to the 80188 may be generated, depending upon the setting of the crcsu unmask bit of tir6. the crcs bit of tir4 always indicates when the crc has been appended to an outgoing frame, regardless of the state of the crcsu bit. the crc32 polynomial is x32+x26+x23+x22+x16 +x12+x11+x10+x8+x7+x5+x4+x2+x+1; the initial condition of the crc32 calculation is ffff ffffh; and the final remainder of the crc32 operation is debb 20e3h. the crc8 polynomial is x8+x5+x+1; the initial condi- tion of the crc8 calculation is ffh; and the final ex- pected remainder of the crc8 operation is 66h. tx status tir9 provides bits that indicate the current state of the AM79C930 device with respect to the transmission of a frame. for example, the tir9 bits indicate the number of bytes currently in the tx fifo and whether or not the transmission is active. start of frame delimiter detection automatic start of frame delimiter (sfd) detection is built into the AM79C930 device's tai subunit. start of frame delimiter length may be defined as 0 bytes, 1 byte, 2 bytes or 3 bytes. the length of sfd is set with the sd bits of tcr0. the pattern of the sfd is programma- ble. the sfd registers tcr8, tcr9, and tcr10 are programmed by the user with the sfd pattern to be matched. register status bits with associated interrupt capability exist for both antenna lock and start of frame delimiter detected. the various register status and interrupt unmask bits are located in tir4, tir5, tir7, tir9, and tir26. the fdet output pin signals the start of frame boundary to external logic and operates during both rx and tx. start of frame detection is al- ways calculated based upon network ordering of bits and is therefore independent of the setting of the wns bit (big vs little endian bit ordering control) of tcr3. the start of frame delimiter search may be performed by external logic, and the result passed into the AM79C930 device through the user6/irq5/extsdf/ exta2dst pin when the enxsdf bit of tcr28 has been set to 1. see the multi-function pin section for more detail. rx data parallelization once the rx preamble and start of frame delimiter have been located, subsequent bits in the serial rx data stream are converted to parallel byte format and moved into the rx fifo. as the rx fifo fills with data, the tai will request rx data byte removal by asserting the drq0 input of the embedded 80188 core. the rxfc bits of tir17 contain the current byte count of the rx fifo. rx fifo tai contains individual fifos for rx and tx operations. the rx fifo indicates a non-empty state by signaling a request for data on the drq0 input of the 80188 embed- ded core. the drq0 output of the tai subunit is active if the rx fifo condition is met, regardless of the state of the rxs bit of tir16. rx fifo dma activity is prevented by disabling the dma0 controller in the 80188. the rx fifo holds a maximum of 15 bytes of data. the number of bytes of data residing in the rx fifo is indi- cated in tir17. tai automatically removes the pream- ble and start of frame delimiter from the incoming frame. any phy header that has been passed from the transceiver to the AM79C930 device will be preserved in the fifo, provided that the phy header is located after the preamble and sfd fields. rx crc checking crcs are automatically checked on arriving frames. registers in the tai indicate where crc8 and crc32 p r e l i m i n a r y amd 51 AM79C930 values were found to be correct. these register values can be used to determine the end of a received frame. when good crc values are found, these may be sig- naled to the 80188 core through interrupt bits in tir5. the crc32 polynomial is x32+x26+x23+x22+x16 +x12+x11+x10+x8+x7+x5+x4+x2+x+1; the initial condition of the crc32 calculation is ffff ffffh; and the final remainder of the crc32 operation is debb 20e3h. the crc8 polynomial is x8+x5+x+1; the initial condi- tion of the crc8 calculation is ffh; and the final ex- pected remainder of the crc8 operation is 66h. rx status reporting tir11 provides bits that indicate the current state of the AM79C930 device with respect to the reception of a frame. for example, the tir11 bits indicate the number of bytes currently in the rx fifo and whether or not a reception is active. bit ordering both big and little endian support is available for trans- mit and receive operations. the default mode is little endian. the operational mode is selected with the wns bit of tcr3. only fifo data is affected by the wns set- ting. no other register information is swapped. rssi a/d unit several modes of operation are possible with the AM79C930 a/d subunit. the following two paragraphs describe the basic internal mode of operation. following this description is a list of the additional modes and de- scriptions of each. for programming information, refer to the adda bit description under tir26[2]. the tai contains a configurable rssi a/d unit that al- lows externally supplied analog values to be converted to 7-bit digital values. two a/d analog input pins are pro- vided (adin1, adin2). the active input may be selected with the srcs (source select) bit in tir26. the conver- sion time of the internal a/d converter is approximately 600 ns. the frequency of sample conversion is con- trolled with the antenna diversity timer register (tcr4). a/d converter output values are available at the sar[6:0] output pins for external use. a/d converter output values are available to firmware by reading from tir27. the result of the a/d conversion is used by inter- nal logic to perform clear channel assessment (cca) and antenna diversity tests. a reference input (adref) is supplied which allows the user to set the upper range limit on the a/d converter. the rssi a/d unit's output may be used by the cca logic and by the antenna diversity logic, depending upon the setting of the urssi bit of tcr28. if the urssi bit is set to 1, then the a/d conversion process begins after a programmable delay following an antenna diversity antenna switching operation. (the switching operation is periodic, with the period being set with the antenna diversity timer register of tcr4.) the delay from antenna switch to the beginning of the a/d conver- sion operation is programmed in the rssi sample start register (tcr24). the converted rssi value is then compared against the rssi lower limit value that is programmed into tir28. the current rssi limit com- parison test result may be read from the rsalt bit (rssi above limit) of tir28. the result of this compari- son test is fed to the cca decision logic and to the stop diversity decision logic when the urssi bit of tcr28 is set to 1. there are three submodes to the basic internal a/d converter mode: internal_a mode disables the sar pins (tcr25[5] = ensar = 0) internal_b mode allows the converted value to be driven onto the sar pins. (tcr25[5] = ensar = 1) internal_c mode allows an external circuit to control the timing of the a/d sample and convert operation in order to synchronize the internal AM79C930 de- vice's a/d operation with the operations of an exter- nal antenna selection scheme. this mode is selected with the uxa2dst bit of tcr25[7]. normally, the a/d conversion starts when the antenna dwell timer counts down to the value programmed in the sample start field of tcr24 (ss field). the antenna dwell timer repeats its cycle every adt[5:0] time steps, forever. if a satisfactory antenna is found, then the an- tenna switching ceases, but rssi testing continues to provide input to the cca logic at the end of each dwell. however, when uxadtst is set to 1, then the a/d con- verter will sample and convert whenever a rising edge appears on the user6/irq5/extsdf/exta2dst pin. the conversion process will occur over the time pro- grammed in the tcr25 a2dt field. this function allows an external circuit to synchronize the function of the AM79C930 a/d converter to the external circuit's peri- odic requirements. a/d converted values will be avail- able on the sar output pins, provided that the ensar bit of tcr25 has been set to a 1. in addition to the internal a/d modes, there are two ex- ternal modes, one for a/d and one for d/a: external a/d mode causes the adin1 and adin2 pins to become outputs, which are then used to control the power cycling and conversion of an external a/d device. the sar pins are used as inputs in this mode to allow the externally converted value to be driven back into the AM79C930 device, so that it may be used in the cca and antenna diversity logic circuits. in this mode, adin1 functions as the power control signal. adin1 be- comes active at the beginning of the a/d cycle, with a period as specified in the antenna diversity timer amd p r e l i m i n a r y 52 AM79C930 register of tcr4. adin2 becomes active after adin1 by the amount of delay specified in the rssi sample start time of tcr24. adin2 remains active for the time pro- grammed in the a2dt register (tcr25). the converter output should be connected to the sar pins, which act as inputs in this mode. external d/a mode allows the user to connect an exter- nal d/a converter to the AM79C930 device. the sar pins function as outputs and values written to the sar register (tir27) will be driven onto these pins for con- version by the external d/a device. the following table indicates the programming required in order to effect each mode of the a/d section of the AM79C930 device: adda enext ensar uxa2dst a/d tir26[2] tcr25[6] tcr25[5] tcr25[7] mode 0 0 0 0 internal_a 0 0 0 1 reserved 0 0 1 0 internal_b 0 0 1 1 internal_c 0 1 0 x external 0 1 1 x reserved 1 x 0 x reserved 1 x 1 x d/a mode physical header accommodation the AM79C930 device can accommodate physical header information by delaying the start of crc8 and crc32 calculations on outgoing and incoming frames, until a specified number of bytes beyond the start of frame detection has become asserted. the length of the physical header may be anywhere from 0 to 15 bytes as indicated by the value in the pfl bits of tcr3. dc bias control an optional dc bias control circuit exists within the AM79C930 device. this circuit may be disabled through software control. the circuit uses 16-bit block inversion and bit stuffing to insure a proper dc balance to the out- going signal on transmit. receive signals will automati- cally have the dc bias control removed before further operations inside of the AM79C930 device. bit stuffing may begin with the first bit transmitted after sfd, or at the beginning of a programmable number of byte times following the sfd. receive frames may be de-stuffed in a similar manner. dc bias control may be disabled for transmit through a control bit located in tcr1. dc bias control may be disabled for receive through a control bit located in tcr3. bit stuffing start control is located in tcr2 [7]. baud determination logic the tai contains baud determination logic that sam- ples the incoming bit stream to determine the data rate. the result of the baud determination is used in making decisions regarding clear channel assessment and in selecting an antenna. the baud determination logic functions as follows: baud determination testing is performed on a periodic basis, where the period is determined by the antenna diversity time of tcr4. baud determination is intended to be alternately performed on up to two separate anten- nas. the antenna diversity decision logic is coupled to the baud determination logic in such a manner that each successive set of baud determination tests is per- formed on alternating antenna selections. baud deter- mination continues for cca when an antenna is chosen, but baud detect results will not affect antenna selection once an antenna has been locked. baud detect tests continue with the periodicity of the dwell timer. antenna diversity switching ceases when a satisfactory antenna has been found. see the section on automatic antenna diversity logic for antenna selection criteria and testing. antenna selection testing resumes following the asser- tion of either the rxres bit (rx reset) of tir16 or the rxs bit (rx start) of tir16. this action causes the dwell timer to reset to the value found in tcr4 [5:0] and then to resume. because antenna switching can cause transient noise to appear at the rxd input of the AM79C930 device, the start of baud determination testing is delayed for a pe- riod of time immediately following the antenna switching process. in order to accommodate different transceiver/ antenna settling times, the amount of test start delay is programmable through the baud detect start timer of tcr16. therefore, the duty cycle of the baud determi- nation test period (i.e., the portion of the period during which baud test measurements are performed) is equal to the antenna diversity time of tcr4 minus the value of the baud detect start time of tcr16, minus an addi- tional three clkin periods (6 clkin periods if clkgt20=1). the three clkin periods are used for fi- nal calculations of baud determination, clear channel assessment, and antenna selection once a set of meas- urements has been taken and before a new cycle is al- lowed to begin. the baud determination measurement process is con- ducted as follows: two counters track the separation between adjacent falling edges and adjacent rising edges of incoming receive data. one counter measures the separation between adjacent falling edges of incoming receive data, and the other counter measures the separation between adjacent rising edges of incoming receive data. measurement resolution is equal to the clkin pe- riod with the clkgt20 bit of mir9 set to 0, and p r e l i m i n a r y amd 53 AM79C930 resolution is equal to twice the clkin period when the clkgt20 bit of mir9 is set to 1. (for a 1 mb data rate with clkin = 20 mhz and clkgt20 = 0, resolution is 50 ns.) after each pair of rising edges is detected, the value of the rising edge separation counter is compared against the baud detect upper limit register value (tcr17) and also against the baud detect lower limit register value (tcr18). if the rising edge counter value is between these limits, then a good counter is incre- mented. if the rising edge counter value is outside of these limits, then a fail counter is incremented. a similar comparison is made whenever the falling edge detection circuit locates a pair of falling edges. the good counter and the fail counter are shared by both the rising edge and falling edge measurement circuits. both rising edge measurements and falling edge meas- urements will contribute to the total good and fail counts during any baud determination cycle period. note that the falling and rising edge separation counters begin counting at 0 and count up to 30 decimal and then wrap back to 10 decimal before continuing. this means that all multiples of 20 counts are aliased to a final counter indication of 20. neither of the rising or falling edge separation counters is accessible to the user. at the end of any baud determination cycle, the value in the good counter is compared against the baud de- tect accept count for carrier sense (tcr19). if the good count is less than the value of tcr19, then the baud detect determination of carrier sense is uncondi- tionally false. if the good count exceeds the value of tcr19, then the good count is compared against the value of the baud detect ratio register (tcr21) multi- plied by the fail count . if the good count exceeds this value, then the baud detect determination of carrier sense is true. the baud detect determination of car- rier sense may, in turn, be used in the final determina- tion of carrier sense (clear channel assessment), depending upon the setting of the ubdcs bit of tcr28. at the end of any baud determination cycle, the value in the good counter is compared against the baud de- tect accept count for stop diversity (tcr20). if the good count is less than the value of tcr20, then the baud detect determination for stop diversity switching is unconditionally false. if the good count exceeds the value of tcr20, then the good count is compared against the value of the baud detect ratio register (tcr21) multiplied by the fail count . if the good count exceeds this value, then the baud detect determi- nation for stop diversity is true. the baud detect de- termination for stop diversity may in turn, be used in the final determination of antenna selection, depending upon the setting of the ubdsd bit of tcr28. clear channel assessment logic the AM79C930 device gathers cca information from one of two possible sources. one source is the AM79C930 device's internal cca logic, which is de- scribed in the following paragraphs. the other possible cca source is externally computed cca information, which is then passed into the AM79C930 device through the user5/irq4/extchbsy pin. regardless of the source of cca information, a path through the AM79C930 tai section is provided allowing the embed- ded 80188 controller to either poll the status of the cca result or to be interrupted by any change to the cca status, or to be interrupted whenever the cca status changes to the busy state. selection of cca source is through the enxchbsy bit of tcr15. the tai contains cca logic that relies on two inputs to determine whether or not a carrier is present on the me- dium. one, both, or none of the two inputs may be se- lected to determine whether or not a carrier is present. one input that may be used to determine carrier sense is the result of the baud determination of carrier sense as described in the baud determination logic section. the other input used by the cca logic is whether or not the value of the converted rssi input exceeds a pro- grammed lower limit (rssi lower limit of tir28). note that baud determination of carrier sense meas- urements are made on a periodic basis where the period and duty cycle of the measurements depends upon the settings of the antenna diversity timer (tcr4) and the baud detect start timer (tcr16). either input or both inputs may be used to make the cca decision. each input to the cca logic is enabled by a specific bit of tcr28. the ubdcs bit of tcr28 is used to select/deselect the baud determination of carrier sense for use in cca decisions, and the urssi bit of tcr28 is used to select/deselect rssi information in cca decisions. note that urssi bit of tcr28 is also used to select/deselect rssi information for use in stop diversity decisions. the possible cca results are as follows. amd p r e l i m i n a r y 54 AM79C930 cca result ubdcs urssi baud detect carrier rssi >= rssi (chbsy bit tcr28:1 tcr28:0 sense decision lower limit of tir26) 0 0 don't care don't care chbsy = true 0 1 don't care yes chbsy = true 0 1 don't care no chbsy = false 1 0 true don't care chbsy = true 1 0 false don't care chbsy = false 1 1 true yes chbsy = true 1 1 true no chbsy = false 1 1 false yes chbsy = false 1 1 false no chbsy = false the current cca result is reported in the chbsy bit of tir26. a rising edge of chbsy will set the busy channel found (bcf) bit of tir5. this bit may serve as an inter- rupt to the 80188 core, or the interrupt due to this bit may be masked and the bit can be polled by the 80188 core. the cca result is also reported in the chbsyc bit of tir4. this bit reports a change in state of the carrier sense. this bit may serve as an interrupt to the 80188 core, or the interrupt due to this bit may be masked and the bit can be polled by the 80188 core. the current rssi limit comparison test result may be read from the rsalt bit (rssi above limit) of tir28. the cca result has no effect on the transmit state ma- chine operation. that is, if the cca result is chbsy = true and the txs bit (transmit start) of tir8 has been set to a 1, then the transmit state machine will proceed with execution of its transmission sequence. determina- tion of exactly when to begin transmission is the respon- sibility of the firmware that sets the txs bit of tir8, based upon input derived from the chbsy bit of tir26 and other considerations (such as nav value, backoff timer, etc.). automatic antenna diversity logic the tai contains automatic antenna diversity logic that relies on carrier sense determination in order to select a satisfactory antenna for frame reception. the general function of the antenna diversity logic is as follows: the automatic antenna diversity logic switches the antslt and antslt pins between two different anten- nas repeatedly at a programmable periodic rate. meas- urements of signal strength and baud determination testing are performed on each antenna. antenna diver- sity switching and test measurements continue until the combination of the test outcomes dictates a stop to di- versity switching. at such a point, a satisfactory antenna has been found, antenna switching will cease and the selected antenna will be used for reception until the re- ceive reset (rxres) bit of tir16 is set, or until the receive start (rxs) bit of tir16 is set, or a hard reset, or a soft reset. baud detection tests continue during antenna lock time, using the same periodicity (i.e., the dwell timer), even though antenna switching has stopped. these baud tests provide input for the cca logic. an antenna is deemed satisfactory when the combina- tion of inputs to the stop diversity decision logic is true. the stop diversity decision is based upon the value of one or two input conditions, where the user may choose which conditions are examined. the following are the two inputs that may be used for stop diversity decisions: one possible input to the stop diversity decision logic is the baud detect for stop diversity determination as described in the baud determination section and summarized here. the baud detect for stop diversity determination is made by making multiple measure- ments of the separation between adjacent (and sameC direction) bit stream edge transitions (baud detect tests), then comparing the measured rate of edge transi- tions against programmed limits and tallying the number of passes and failures of these tests, checking to see that the total number of passed tests exceeds a given lower limit, and finally, checking that the ratio of passes to fails exceeds a given threshold ratio. if this final result is true, then the baud detect for stop diversity is con- sidered to be true. note that baud determination of stop diversity meas- urements are made on a periodic basis where the period and duty cycle of the measurements depends upon the settings of the antenna diversity timer (tcr4) and the baud detect start timer (tcr16). the dwell timer never stops running (unless set to 0). the second possible input to the stop diversity decision logic is the result of a comparison of the rssi converted value against a pre-programmed lower limit. if the measured rssi input value exceeds the programmed lower limit, then the result of this test is considered to be true. the two tests mentioned above may be separately selected/deselected to serve as inputs to the stop p r e l i m i n a r y amd 55 AM79C930 diversity decision logic for determining if a satisfactory antenna has been found. these inputs to the stop di- versity decision logic are enabled by specific bits of tcr28. the ubdsd bit of tcr28 is used to select/ deselect the baud determination of stop diversity for use in stop diversity decisions and the urssi bit of tcr28 is used to select/deselect rssi information in stop diversity decisions. note that the urssi bit of tcr28 is also used to select/deselect rssi information for use in cca decisions. the possible stop diversity results are shown in the table below. the current stop diversity result is reported in the antlok bit of tir26. a rising edge of antlok will set the aloki (antenna lock interrupt = diversity switching stopped) bit of tir5. this bit may serve as an interrupt to the 80188 core, or the interrupt due to this bit may be masked and the bit can be polled by the 80188 core. the antenna diversity switching is signaled with the antsw bit of tir4. this bit reports a change in the an- tenna selection. this bit may serve as an interrupt to the 80188 core, or the interrupt due to this bit may be masked and the bit polled by the 80188 core. the current antenna selection may be read from the antslt bit of tir26. the current rssi limit comparison test result may be read from the rsalt bit (rssi above limit) of tir28. automatic antenna diversity switching may be disabled through appropriate setting of the antsen bit of tir26. manual setting of the antenna selection is then allowed through the ants bit of tir26. txc as input for typical transceiver connections, the signal txc is defined as an input to the transceiver. however, for some transceiver connections, the signal txc is de- fined as a transceiver output . the AM79C930 device can accommodate both types of transceivers by allow- ing the txc pin to be defined as either output or input. in the case where the txc pin is as output from a trans- ceiver, the txcin bit of tcr30 must be set to a 1 in order to change the direction of the txc signal. when this is done, a 16-bit serial-fifo is added into the path of the tx data in order to accommodate a small amount of possible mismatch between the transceiver's txc fre- quency and the AM79C930 device's internal txc fre- quency. when this fifo is inserted into the transmit data stream, an additional delay of 8-bit times is incurred between the assertion of the txs bit of tir8 and the as- sertion of the first transceiver transmit control signal in the transmit control sequence. if the mismatch between the transceiver's txc fre- quency and the AM79C930 device's txc frequency is too large, then a serial-fifo overflow or underflow con- dition may occur. when this situation arises, an error will be indicated by the atfo or atfu bits of tcr11. ieee 1149.1 test access port interface an ieee 1149.1 compatible boundary scan test access port (tap) is provided for board level continuity test and diagnostics. all digital input, output, and input/output pins are tested. adref, trst , tck, tms, tdi, tdo, and pmx2 pins are not included in the boundary scan test. stop diversity baud detect stop result ubdsd urssi stpen stop diversity rssi >= rssi (antlok bit tcr28[2] tcr28[0] tcr28[3] decision lower limit of tir26) x x 0 don't care don't care antlok = false 0 0 1 don't care don't care antlok = true 0 1 1 don't care yes antlok = true 0 1 1 don't care no antlok = false 1 0 1 true don't care antlok = true 1 0 1 false don't care antlok = false 1 1 1 true yes antlok = true 1 1 1 true no antlok = false 1 1 1 false yes antlok = false 1 1 1 false no antlok = false amd p r e l i m i n a r y 56 AM79C930 the following is a brief summary of the ieee 1149.1 compatible test functions implemented in the AM79C930 device: boundary scan circuit the boundary scan test circuit uses five pins: trst, tck, tms, tdi, and tdo. these five pins are collec- tively labeled the tap. the boundary scan test circuit in- cludes a finite state machine (fsm), an instruction register, and a data register array. internal pull-up resis- tors are provided for the tdi and tms pins. the tck pin must not be left unconnected. tap fsm the tap engine is a 16-state fsm, driven by the test clock (tck) and the test mode select (tms) pins. this fsm is in its reset state at power up or after h_reset. the trst pin is supported in order to ensure that the fsm is in the test_logic_reset state before test- ing is begun. supported instructions in addition to the minimum ieee 1149.1 requirements (bypass, extest, and sample instructions), one additional instruction (idcode) is provided as addi- tional support for board level testing. all unused instruc- tion decodes are reserved. instruction name instruction code mode selected data register description extest 0000 test bsr external test id_code 0001 normal id reg id code inspection sample 0010 normal bsr sample boundary reserved 0011C1110 reserved reserved reserved bypass 1111 normal bypass bypass scan instruction register and decoding logic after h_reset or s_reset, the idcode instruction is always loaded into the ieee 1149.1 register. the de- coding logic gives signals to control the data flow in the data registers according to the current instruction. boundary scan register (bsr) each bsr cell has two stages. a flip-flop and a latch are used for the serial shift stage and for the parallel output stage, respectively. there are four possible operation modes in the bsr cell: 1 capture 2 shift 3 update 4 system function other data registers (1) bypass register (1 bit) (2) device id register (32 bits) (3) inscan0 device id register contents: bits 31C28: version bits 27C12: part number (0010 1000 0101 0000) bits 11C1: manufacturer id. the 11 bit manufacturer id code for amd is 00000000001 in accor- dance with jedec publication 106-a. bit 0: always a logic 1 this is an internal scan path for amd internal testing use. power saving modes power down function the AM79C930 biu includes five registers that are used to invoke a power-down function that will support the ieee 802.11 (draft) specified power down by allowing variable lengths of power-down and power-up time. the registers include the processor interface register (mir0), which contains the power down command bit, a power down length count set of registers (mir2,3,4), and a power up clock timer (mir1) register. the power down sequence is executed by the firmware running on the embedded 80188, either independently, or in response to a request from the host. in the pcmcia p r e l i m i n a r y amd 57 AM79C930 mode, the host requests a power down by writing to the power down bit (bit 2) of the pcmcia card configura- tion and status register. in the isa plug and play mode, the host requests a power down by writing to the isa power down bit, bit 7 of sir3. in either case, the power down request will generate an interrupt to the 80188 em- bedded core. in response to the interrupt, the 80188 core should be programmed to perform a power down sequence, as follows: to power down the AM79C930 device, the 80188 core should write a time value to the power down length count registers. this time value is the intended duration of the power down period. then the 80188 core should write a time value to the power up clock timer regis- ters. this time value is the time needed for the buffered clkin signal to return to stable operation from a stopped state. then the 80188 core should write to ap- propriate tir registers to power down the transceiver. the 80188 core should now signal an interrupt to the host that it is about to enter the power down mode. this communication is necessary, since some of the AM79C930 system resources will not be available dur- ing power down mode, and the driver should not attempt accesses to the unavailable resources, or else an unac- ceptably long waiting period will occur before the AM79C930 device finally wakes up and responds to the access. the host should respond to the 80188-generated interrupt, and the 80188 will respond by writing a 1 to the power down bit in the processor in- terface register (mir0). the power down command will cause the internally routed clkin signal to the 80188 and the tai to stop running, thereby, bringing the 80188 itself into a power savings mode. at this point in the sequence, the driver software will no longer have ac- cess to the sram and flash memory devices. only the pcmcia ccr registers and sir0, sir1, sir2 and sir3 will remain accessible to the host. when the power down command is executed, the pwrdwn output will become active. this output can be used to power down additional devices which are part of the entire AM79C930-based subsystem, such as a radio transceiver. (note that the clkin clock signal to internal AM79C930 circuits will be gated off inside of the AM79C930 device, even when the external oscillator continues to drive the AM79C930 clkin input.) in the power down mode, slave accesses to the AM79C930 device will become limited to the pcmcia card configuration option register, the pcmcia card configuration and status register, and sir0, sir1, sir2, and sir3 if the AM79C930 device is in pcmcia mode. all other registers will be inaccessible, including sram and flash memory locations either through the memory window or through sir4, sir5, sir6, or sir7. (note that a cis read operation will cause power down exit, but will proceed normally.) if the AM79C930 device is operating in the isa plug and play mode, then sir0, sir1, sir2, and sir3 registers will be the only locations that are still accessible when the AM79C930 device is in the power down mode. sir4, sir5, sir6, and sir7, plug and play registers, and sram and flash memory locations will not be accessi- ble in the power down mode when isa plug and play mode has been selected. this means that plug and play state changes will not be possible in the power down mode. when the power down command is executed, the clock to most of the circuits of the device is suspended while power is maintained, such that all state information is preserved. outputs that were driving active high or ac- tive low signals at the time of execution of the power down command will continue to hold in the state that they were in at the time of execution of the power down command. outputs that were held in a high impedance state will remain in a high impedance state. note that some outputs may still change state, as some sections of the device are not affected by power down (e.g., the system interface signals that are used to access the pcmcia configuration registers and sir0, sir1, sir2, and sir3). transitions on device inputs which lead to circuits that are affected by the power down will not be seen by the circuit, since the circuit is powered down. when the power down mode is exited, the internally sus- pended clock will resume and logical operations will continue from the point of suspension with no loss of state information. when the power down length counter reaches the value of the power up clock timer, then the pwrdwn output will be deasserted. when the power down length counter reaches 0, then the signal on the clkin input to the AM79C930 will once again be sent to all parts of the device. the time between the deassertion of pwrdwn and the reapplication of the clkin to internal circuits allows the clock to stabilize before it is distrib- uted to the 80188 core and the tai. a discrete power up timer, which would indicate the time duration that the AM79C930 device should remain awake, is not included in the AM79C930 device, but a firmware implementation of such a function is possible by using the free count of mir5, mir6, and mir7 and/or 80188 controller timers. writing a 1 to the power down bit of the pcmcia card configuration and status register will cause a request for a power down to be generated to the 80188 core via an interrupt bit in mir0. the decision to power down will be made by the 80188 controller, and the actual power down command will be executed by the 80188 controller by shutting off the transceiver and any other resources and then writing to the power down command bit (pdc) of mir0. amd p r e l i m i n a r y 58 AM79C930 writing a 1 to the power down bit of the isa power down bit of sir3 will cause a request for a power down to be generated to the 80188 core via an interrupt bit in mir0. the decision to power down will be made by the 80188 controller, and the actual power down command will be executed by the 80188 controller by shutting off the transceiver and any other resources and then writing to the power down command bit (pdc) of mir0. writing a 0 to the power down bit of the pcmcia card configuration and status register will cause the power down mode to be exited early by forcing the pdlc value to 0. because of this transition to 0, the puct value will most likely not be encountered, and no power up ramp time will occur (i.e., the pwrdwn signal will be deas- serted at the same time that the clkin is reapplied to the internal circuitry.). writing a 0 to the isa power down bit of sir3 will cause the power down mode to be exited early by simulating the effect of the power down length counter expiring. writing a 1 to the exit power down bit of sir0 will cause the power down mode to be exited early by forcing the pdlc value to 0. because of this transition to 0, the puct value will most likely not be encountered, and no power up ramp time will occur (i.e., the pwrdwn signal will be deasserted at the same time that the clkin is reapplied to the internal circuitry.). performing a cis read operation while the AM79C930 device is in the power down mode will cause an early exit of the power down mode in exactly the same man- ner as if the pcmcia card configuration and status register power down bit had been reset by writing a 0 to it. applicability to ieee 802.11 power down modes the power down functionality described above can be applied to the ieee 802.11 (draft) power down modes by setting appropriate time values in the power down length count register. this allows the AM79C930 de- vice to power up at the ieee 802.11 (draft) specified tim- ing intervals in order to listen to the network for tim and dtim messages. after listening for a specific amount of time, the AM79C930 device can interrupt the driver soft- ware with the intent of requesting the driver to re-initiate the power down sequence. the free-running counter can be used to calculate the proper power down length count register values for each power down cycle. software access the AM79C930 device is directly driven by two pieces of software: (1) the device driver, which runs on the host machine's cpu, performs transfers of data between the upper layers of the application and the AM79C930 de- vice; and (2) the AM79C930 mac firmware, which runs on the embedded 80188 cpu, performs ieee 802.11 (draft) mac protocol functions and sends status infor- mation to the device driver. the device driver communi- cates with the AM79C930 device through the system interface, usually by reading and writing to the sram, with occasional accesses to AM79C930 device registers. the AM79C930 device appears to the device driver as a series of i/o mapped registers, memory-mapped sram, and flash memory. the mac firmware uses most of the AM79C930 device registers, the sram, and the flash memory to perform the ieee 802.11 (draft) mac functions. the AM79C930 device driver also uses the sram to pass command and status information to and from the AM79C930 device. AM79C930 system interface resources driver interaction with the AM79C930 device takes place through the system interface. the purpose of the AM79C930 device driver is to move data frames in and out of the AM79C930-based wireless communications system. the device driver will move outgoing data frames into shared memory space and then pass a command to the AM79C930 device indicat- ing that the outgoing data is present and ready for trans- mission. the device driver will respond to interrupts from the AM79C930 device indicating that incoming data has been placed into shared memory by the AM79C930 device and is present and ready for proc- essing by the device driver. the AM79C930 device also uses the interrupt to indicate other changes in AM79C930 device status. commands other than trans- mit may be passed to the AM79C930 device by the driver. in order to accommodate these basic functions of the driver, the AM79C930 device includes a number of com- mand and status registers as well as direct system inter- face access to up to 128k of shared memory space (sram). the device driver also has access to the 128k of flash memory space that is used to store the firmware for the embedded 80188 core. the following sections describe the resources available to the device driver through the system interface. later sections will describe the resources available to the mac firmware through the 80188 embedded core. pcmcia mode resources the first table indicates the range of i/o and memory addresses to which the AM79C930 device will respond while operating in the pcmcia mode: p r e l i m i n a r y amd 59 AM79C930 AM79C930 device pcmcia mode resource requirements common common attribute attribute memory range memory size i/o range i/o size memory range memory size 0000h C 7fffh 32 kbytes 0000h C 0027h 40 0000h C 0803h 2 k+4 bytes or or or 0 bytes 0000h C 000fh 16 bytes the i/o range is adjusted through bit 2 (eiow = expand i/o window) of sir1 = bank switching select register). note that since the AM79C930 device's memory mapped resources are all accessible through the local memory address register and i/o data ports (sir2,3,4,5,6,7), it is possible to assign the AM79C930 device no memory space. (this is accomplished by setting the memspace field of the tpce_fs byte of the configuration table entry tuple to 00b. this will inform the pcmcia configuration utility that the AM79C930-based design does not require any com- mon memory space.) by assigning no memory space to the AM79C930 device, the AM79C930 device will become an i/o only device. such an arrangement may be convenient for systems in which there is not enough total available memory space to allow the AM79C930 device to use a full 32k block of memory. note that when this option is chosen, the total amount of bus bandwidth required to perform all of the necessary accesses to the AM79C930-based design will be in- creased somewhat, because of the indirect nature of the i/o method of access to AM79C930-based resources. note that the AM79C930 device always decodes the lowest 6 bits of address when an i/o access is performed with the AM79C930 device's ce1 signal ac- tive. this means that there is aliasing of addresses in i/o space. this decode function is unaffected by the setting of the sir1[2:0] register bits. pcmcia common memory resources while the common memory space of the AM79C930 device only accommodates access to 32 kbytes of memory, the AM79C930 device uses device select and bank select bits in sir1 in order to access a total of 256k of memory space. note that pcmcia accesses to common mem- ory locations 7c00hC7fffh (1k total space) will some- times correspond to the same physical locations as pcmcia accesses to attribute memory locations 0000hC07ffh (2k total space), i.e., the correspon- dence will occur only when the device and bank select bits of sir1 are pointing at the upper page of the 128k flash memory address space. (note that for attribute memory accesses, only the even-valued addresses are defined to exist. therefore, 2k total attribute memory addresses have been mapped to 1k of physical space in the flash memory.) the following table indicates the mapping of the 256 kbytes of physical memory space into the 32 kbytes of common memory: AM79C930 device pcmcia mode common memory map pcmcia address in common memory sir1[5:3] size of space physical memory 0000h C 7fffh 000 32 kbytes sram memory 0 0000h C 0 7fffh 0000h C 7fffh 001 32 kbytes sram memory 0 8000h C 0 ffffh 0000h C 7fffh 010 32 kbytes sram memory 1 0000h C 1 7fffh 0000h C 7fffh 011 32 kbytes sram memory 1 8000h C 1 ffffh 0000h C 7fffh 100 32 kbytes flash memory 0 0000h C 0 7fffh 0000h C 7fffh 101 32 kbytes flash memory 0 8000h C 0 ffffh 0000h C 7fffh 110 32 kbytes flash memory 1 0000h C 1 7fffh 0000h C 7fffh 111 32 kbytes flash memory 1 8000h C 1 ffffh total: 256 kbytes amd p r e l i m i n a r y 60 AM79C930 some of the AM79C930 device's pcmcia common memory locations have predefined uses and, therefore, are not freely available to the device driver. the following table indicates restricted space within pcmcia common memory map of the AM79C930 device: AM79C930 device pcmcia mode common memory restricted space pcmcia address size of physical memory and in common memory sir1[5:3] restricted space description of reserved use 0000h C 03ffh 000 1 kbytes sram memory 0 0000h C 0 03ffh this space is reserved for the interrupt vector table of the embedded 80188 core. 0400h C 041fh 000 32 bytes sram memory 0 0400h C 0 041fh this sram space is inaccessible to the 80188 embedded core, since the 80188 core maps the 32 tir registers of the tai into this portion of 80188 memory space. 0420h C 043fh 000 32 bytes sram memory 0 0420h C 0 042fh this sram space is inaccessible to the 80188 embedded core, since the 80188 core maps the mir registers of the biu (pir, pdlc and puct) and xce space into this portion of 80188 memory space. 0440h C 047fh 000 64 bytes sram memory 0 0440h C 0 047fh this sram space is reserved for future use and may be decoded for non- sram purposes in the future. 7c00h C 7fefh 111 1kC16 bytes flash memory 1 fc00h C 1 ffefh these bytes of the flash memory also map into pcmcia attribute memory space 0000h C 03ffh, which is used for storing the cis for the device. therefore, this space cannot be used for non-cis purposes. 7ff0h C 7fffh 111 16 bytes flash memory 1 fff0h C 1 ffffh these 16 bytes of flash memory space are reserved because they are the location of the embedded 80188 core's instruction pointer following a AM79C930 device reset operation. these 16 bytes must contain the first 80188 instructions. p r e l i m i n a r y amd 61 AM79C930 the sram is intended to serve as a shared memory re- source between the driver operating through the system interface and the 80188 core operating through the AM79C930 memory interface bus. even though sram memory locations 0 0400h through 0 043fh are acces- sible from the system interface, these locations cannot be used for driver-firmware shared memory functions, since they are inaccessible from the 80188 core. pcmcia attribute memory resources the pcmcia standard requires that each pcmcia device contain a card information structure (cis). the cis contains information that is used to provide possible configuration options to the system. the pcmcia standard requires that the first tuple of the cis should be located at attribute memory byte 0h. 1k of flash memory space is mapped into the lowest 2k of pcmcia attribute memory space to accommodate this requirement. since odd addressed bytes of attribute memory are undefined, these addresses are not mapped to the flash memory. the 1k of flash memory space that is mapped to attribute memory space is also visible as common memory. the upper 32 bytes of the 2k of attribute memory space must not be used for pcmcia cis information, since these bytes map to the upper 16 bytes of the flash memory, which will be used by the 80188 core of the AM79C930 as the initial instruc- tion locations after reset. note that the configuration tuple must contain the value 800h for the tpcc_radr field, since the card configuration registers within the AM79C930 device are located at this fixed offset. the pcmcia card configuration registers that are sup- ported are the configuration option register and the card configuration and status register. these two reg- isters are physically located in the bus interface unit and logically exist only in pcmcia attribute memory space. they are located at attribute memory locations 0800h and 0802h, respectively. the location of these registers is fixed. therefore, the information pro- grammed into the cis must give the value 2k (=0800h) as the card configuration registers base address in the tpcc_radr field of the configuration tuple. AM79C930 device pcmcia mode attribute memory map pcmcia address in attribute memory sir1[5:3] size of space physical memory 0000h C 07ffh xxx* 2 kbytes flash memory 1 fc00h C 1 ffffh (even values only) (only 1 k of flash memory is allocated, since odd addressed pcmcia attribute memory locations are undefined) 0800h xxx* 1 byte configuration option register in biu 0801h xxx* 1 byte device responds with undefined data 0802h xxx* 1 byte card configuration and status register in biu 0803h xxx* 1 byte device responds with undefined data 0804h C 7fffh xxx* 30kC2 bytes device may respond to these addresses. see note below. *xxx = don't care note: device will respond to any address in which a11 is equal to 1 and reg , oe , and ce1 are asserted. the only writable pcmcia attribute memory locations are the two card configuration registers at attribute memory locations 800h and 802h. these two registers do not correspond to flash memory locations. these two registers are physically located inside of the biu section of the AM79C930 device. attribute memory locations 0000hC07ffh are mapped directly to flash memory and are, therefore, read-only locations. note that the 2k space of attribute memory 0000hC07ffh are mapped to 1k of flash memory space. since pcmcia defines that only even addressed bytes of attribute memory are defined to exist, only the even addressed 1k of the 2k attribute space is actually physically present. some of the AM79C930 device's pcmcia attribute memory locations have predefined uses and, therefore, are not freely available to the device driver. the follow- ing table indicates restricted space within pcmcia at- tribute memory map of the AM79C930 device. amd p r e l i m i n a r y 62 AM79C930 AM79C930 device pcmcia mode attribute memory restricted space pcmcia address in attribute memory sir1[5:3] size of restricted space physical memory and description of reserved use 7fe0h C 7fffh 111 32 bytes of attribute flash memory 1 fff0h C 1 ffffh memory, 16 bytes of actual these 16 bytes of flash memory space are reserved flash memory space because they are the location of the embedded 80188 core's instruction pointer following a AM79C930 device reset operation. these 16 bytes must contain the first 80188 instructions. pcmcia i/o resources the AM79C930 device oc- cupies either 16 or 40 bytes of i/o space, depending upon the setting of the eiow bit (bit 2 of the bss register (sir1)). the i/o space of the AM79C930 contains the general configuration register, the bank switching se- lect register, and the set of 32 tir registers. addition- ally, all AM79C930 resources are accessible through i/o accesses, i.e., all memory structures are accessible through the local memory address and i/o data ports (sir2,3,4,5,6,7). the local memory address port plus sir1[5:3] function together as a pointer to the memory resources of the AM79C930 device. sir1[5] determines the device selected (sram or flash), and sir1[4:3] and lma[14:0] supply the address to the selected device whenever the i/o data port is read or written. whenever any of the i/o data ports is accessed, then the local memory address port value is automatically incre- mented by a value of 1. note that the AM79C930 device always decodes the lowest 6 bits of address when an i/o access is per- formed with the AM79C930 device's ce1 signal active. this means that there is aliasing of addresses in i/o space. this decode function is unaffected by the setting of the sir1[2:0] register bits. p r e l i m i n a r y amd 63 AM79C930 the following table indicates the mapping of all i/o re- sources that are accessible through the AM79C930 pcmcia system interface. note that some resources are physically located within the biu, while others are lo- cated in the tai and still others exist as external flash and sram: AM79C930 device pcmcia mode i/o map resource resource pcmcia resource physical location name mnemonic i/o address sir1[2:0] size of resource sir0: general sir0: gcr 00h xxx* 1 byte biu configuration register sir1: bank switching sir1: bss 01h xxx 1 byte biu select register sir2: local memory sir2: lmal 02h xxx 1 byte biu address [7:0] sir3: local memory sir3: lmau 03h xxx 1 byte biu address [14:8] sir4: i/o data sir4: dpll 04h xxx 1 byte indirect access to port[7:0] sram or flash memory sir5: i/o data sir5: dplm 05h xxx 1 byte indirect access to port[15:8] sram or flash memory sir6: i/o data sir6: dpum 06h xxx 1 byte indirect access to port [23:16] sram or flash memory sir7: i/o data sir7: dpuu 07h xxx 1 byte indirect access to port [31:24] sram or flash memory tir 0C7 C 08h C 0fh 000 1 byte tai each location tir 8C15 C 08h C 0fh 001 1 byte tai each location tir 16C23 C 08h C 0fh 010 1 byte tai each location tir 24C31 C 08h C 0fh 011 1 byte tai each location undefined C 10h C 3fh 0xx na undefined tir 0C31 C 08h C 27h 1x 1 byte tai each location undefined C 28h C 3fh 1xx na undefined *x = don't care isa plug and play mode resources the AM79C930 device fully supports the isa plug and play specification, revision 1.0a, including the plug and play address auto-configuration port, write_data auto-configuration port, read_data auto-configuration port, and 19 of the plug and play configuration registers, as well as providing a mecha- nism for access to flash memory for reading the AM79C930 device's plug and play resource data. the following table indicates the range of i/o and mem- ory addresses to which the AM79C930 device will re- spond when operating in the isa plug and play mode. amd p r e l i m i n a r y 64 AM79C930 AM79C930 device isa plug and play mode memory and i/o resource requirements memory range memory size i/o range i/o size mba*+0000h C 32 kbytes ioba**+0000h C ioba**+000fh 16 bytes mba*+7fffh or and i/o 0279h and i/o 0a79h 0 bytes and i/o 0203h C i/o 03ffh (one byte only) *mba = isa plug and play memory base address **ioba = isa plug and play i/o base address note that since the AM79C930 device's memory mapped resources are all accessible through the local memory address register and i/o data ports (sir2,3,4,5,6,7), it is possible to program the isa plug and play memory base address, and memory upper limit address or range length for descriptor 0, such that the AM79C930 device is assigned no memory space. (this is accomplished by assigning all 0s for both the memory base address and the memory range length value. the isa plug and play utility can be instructed to make this selection through appropriate resource data programming.) by assigning no memory space to the AM79C930 device, the AM79C930 device will become an i/o only device. such an arrangement may be con- venient for systems in which there is not enough total available memory space to allow the AM79C930 device to use a full 32k block of memory. note that when this option is chosen, the total amount of bus bandwidth re- quired to perform all of the necessary accesses to the AM79C930-based system will be increased somewhat, because of the indirect nature of the i/o method of ac- cess to AM79C930-based resources. the AM79C930 device requires the use of a single irq channel. any of the following channels within an isa plug and play system may be utilized by the AM79C930 device: irq 4, 5, 9, 10, 11 or 12. isa plug and play memory resources while the system memory space of the AM79C930 device only accommodates access to 32 kbytes of memory, the AM79C930 device uses device select and bank select bits in sir1 in order to access a total of 256k of memory space. note that isa accesses to memory locations 7c00hC7fffh (1k total space) will sometimes correspond to the same physical locations as isa ac- cesses to plug and play resource data locations 0000hC03ffh, i.e., the correspondence will occur only when the device and bank select bits of sir1 are point- ing at the upper page of the 128k flash memory ad- dress space. the following table indicates the mapping of the 256 kbytes of physical memory space into the 32 kbytes of memory: AM79C930 device isa plug and play mode memory map isa address in memory sir1[5:3] size of space physical memory mba+0000h C mba+7fffh 000 32 kbytes sram memory 0 0000h C 0 7fffh mba+0000h C mba+7fffh 001 32 kbytes sram memory 0 8000h C 0 ffffh mba+0000h C mba+7fffh 010 32 kbytes sram memory 1 0000h C 1 7fffh mba+0000h C mba+7fffh 011 32 kbytes sram memory 1 8000h C 1 ffffh mba+0000h C mba+7fffh 100 32 kbytes flash memory 0 0000h C 0 7fffh mba+0000h C mba+7fffh 101 32 kbytes flash memory 0 8000h C 0 ffffh mba+0000h C mba+7fffh 110 32 kbytes flash memory 1 0000h C 1 7fffh mba+0000h C mba+7fffh 111 32 kbytes flash memory 1 8000h C 1 ffffh total: 256 kbytes *mba = isa plug and play memory base address when accessing AM79C930 memory resources through isa memory cycle accesses, the upper 9 bits of the isa memory address will be used to check for a match of the address range assigned to the AM79C930 device by the plug and play configuration program (i.e., the memory base address = mba, and memory range length). the plug and play configuration program will have written a memory base address value into the memory base address registers (plug and play ports 40h and 41h). the isa plug and play memory base p r e l i m i n a r y amd 65 AM79C930 address needs to be aligned to a 32k boundary in mem- ory space. this alignment requirement should be in- cluded in the resource data that is programmed into the flash device and read by the plug and play configura- tion utility. these conditions must be satisfied, since the AM79C930 device's bus interface unit will only use the upper 9 bits of the isa memory address to determine when an address match has been achieved. some of the AM79C930 device's isa memory locations have predefined uses and, therefore, are not freely available to the device driver. the following table indi- cates restricted space within isa memory map of the AM79C930 device: AM79C930 device isa plug and play mode memory restricted space isa address size of physical memory and in memory sir1[5:3] restricted space description of reserved use mba+0000h C 000 1 kbytes sram memory 0 0000hC0 03ffh mba+03ffh this space is reserved for the interrupt vector table of the embedded 80188 core. mba+0400h C 000 32 bytes sram memory 0 0400hC0 041fh mba+041fh this sram space is inaccessible to the 80188 embedded core, since the 80188 core maps the 32 tir registers of the tai into this portion of 80188 memory space. mba+0420h C 000 32 bytes sram memory 0 0420hC0 042fh mba+043fh this sram space is inaccessible to the 80188 embedded core, since the 80188 core maps the mir registers of the biu (pir, pdlc and puct) and xce space into this portion of 80188 memory space. mba+0440h C 000 64 bytes sram memory 0 0440hC0 047fh mba+047fh this sram space is reserved for future use and may be decoded for non-sram purposes in the future. mba+7c00h C 111 1kC16 bytes flash memory 1 fc00hC1 ffefh mba+7fefh these bytes of the flash memory also map into the isa plug and play resource data space. therefore, this space can not be used for non-resource data purposes. mba+7ff0h C 111 16 bytes flash memory 1 fff0hC1 ffffh mba+7fffh these 16 bytes of flash memory space are reserved because they are the location of the embedded 80188 core's instruction pointer following a AM79C930 device reset operation. these 16 bytes must contain the first 80188 instructions. *mba = isa plug and play memory base address amd p r e l i m i n a r y 66 AM79C930 the sram is intended to serve as a shared memory re- source between the driver operating through the system interface and the 80188 core operating through the AM79C930 memory interface bus. even though sram memory locations 0 0400h through 0 043fh are acces- sible from the system interface, these locations cannot be used for driver-firmware shared memory functions, since they are inaccessible from the 80188 core. isa plug and play i/o resources the AM79C930 device occupies 16 bytes of i/o space. the 40-byte i/o option is not available in the isa plug and play mode of operation. the eiow bit (bit 2 of the bss register (sir1)) will be forced to 0 when the AM79C930 device has been placed into isa plug and play mode. the i/o space of the AM79C930 device contains the general configuration register, the bank switching select reg- ister, and the set of 32 tir registers. additionally, all AM79C930 resources are accessible through i/o ac- cesses, i.e., all memory structures are accessible through the local memory address and i/o data ports (sir2,3,4,5,6,7). the local memory address port plus sir1[5:3] function together as a pointer to the memory resources of the AM79C930 device. sir1[5] determines the device se- lected (sram or flash) and sir1[4:3], and lma[14:0] supply the address to the selected device whenever the i/o data port is read or written. whenever any of the i/o data ports is accessed, then the local memory address port value is automatically incremented by a value of 1. the next table indicates the mapping of all i/o resources that are accessible through the AM79C930 isa system interface. note that some resources are physically located within the biu, while others are located in the tai, and still oth- ers exist as external flash and sram. also note that additional registers for isa plug and play exist in the biu and are indirectly accessed through the plug and play address, write_data, and read_data ports. all resources are 1 byte in width. when accessing AM79C930 i/o resources through isa i/o cycle accesses, the upper 8 bits of the isa system address will be ignored. only the lower 16 bits of address will be used to check for a match of the address range assigned to the AM79C930 device by the plug and play configuration program (i.e., the i/o base ad- dress = ioba). (the plug and play configuration pro- gram will have written an i/o base address value into the i/o base address registers (plug and play ports 60h and 61h) following system boot up and auto-configura- tion.) the isa plug and play i/o base address must be aligned to a 16-byte boundary in i/o space. this align- ment requirement should be included in the resource data i/o port descriptor base alignment field that is programmed into the flash device and read by the plug and play configuration utility. these conditions must be satisfied for proper operation. p r e l i m i n a r y amd 67 AM79C930 AM79C930 device isa plug and play mode i/o map physical isa sir1 resource location of resource name mnemonic i/o address bits [2:0] size resource sir0: general sir0: gcr ioba*+0000h xxx** 1 byte biu configuration register sir1: bank switching sir1: bss ioba+0001h xxx 1 byte biu select register sir2: local memory sir2: lmal ioba+0002h xxx 1 byte biu address [7:0] sir3: local memory sir3: lmau ioba+0003h xxx 1 byte biu address [14:8] sir4: i/o data port [7:0] sir4: dpll ioba+0004h xxx 1 byte indirect access to sram or flash memory sir5: i/o data port [15:8] sir5: dplm ioba+0005h xxx 1 byte indirect access to sram or flash memory sir6: i/o data port sir6: dpum ioba+0006h xxx 1 byte indirect access [23:16] to sram or flash memory sir7: i/o data port [31:24] sir7: dpuu ioba+0007h xxx 1 byte indirect access to sram or flash memory tir 0C7 C ioba+0008h C 000 1 byte tai ioba+000fh each location tir 8C15 C ioba+0008h C 001 1 byte tai ioba+000fh each location tir 16C23 C ioba+0008h C 010 1 byte tai ioba+000fh each location tir 24C31 C ioba+0008h C 011 1 byte tai ioba+000fh each location device does not respond C ioba+0010h C 0xx na na to these accesses ioba+0027h impossible programming of na na 1xx na na sir1 bits (sir1[2] = 0 always in isa plug and play mode) plug and play address ppa 0279h (fixed) xxx 1 byte biu auto-configuration port (write only) plug and play write_data ppwd 0a79h (fixed) xxx 1 byte biu auto-configuration port (write only) plug and play read_data pprd 0203h C 03ffh xxx 1 byte indirect access auto-configuration port (relocatable) to isa plug and (read only) play register set *ioba = isa plug and play i/o base address **x = don't care amd p r e l i m i n a r y 68 AM79C930 isa plug and play register set the AM79C930 de- vice fully supports the isa plug and play specification, revision 1.0a. the AM79C930 device supports the plug and play auto-configuration scheme. the plug and play address auto-configuration port, write_data auto-configuration port, and read_data auto-con- figuration port are all supported and are mapped into isa i/o space as follows: AM79C930 device isa plug and play mode supported auto-configuration ports port name isa (ieee p996) i/o address access address 0279h write only write_data 0a79h write only read_data 0203h C 03ffh (relocatable) read only the location of the read_data auto-configuration port is only fixed within the range 0203hC03ffh. the exact location is determined by a write to the appropriate plug and play auto-configuration port (set read_data auto-configuration port). the write_data port and the read_data port are not active until the initiation key has been sent to the AM79C930 device through the address port. this be- havior conforms to the requirements of the plug and play specification. the AM79C930 device implements the four plug and play configuration states: wait for key, sleep, isolation, and config. all plug and play ports are 8 bits in width. to fully support the plug and play mechanism, the fol- lowing additional register locations are defined within the AM79C930 device. except for the resource data register, these registers are physically located within the biu and are accessed indirectly, through setting the plug and play port address in the plug and play address port (location i/o 0279h) and then by ac- cessing either the write_data port or the read_data port. the 80188 embedded core does not have access to the registers in the following table. p r e l i m i n a r y amd 69 AM79C930 AM79C930 device isa plug and play mode plug and play register set isa plug and play plug and play port register name address physical location set read_data port 00h biu serial isolation 01h biu configuration control 02h biu wake [csn] 03h biu resource data 04h flash memory 1 fc00hC1 fff0h total of 1kC16 bytes. the uppermost 16 bytes of flash memory space are reserved because they are the location of the embedded 80188 core's instruction pointer following an AM79C930 device reset operation. status 05h biu card select number (csn) 06h biu logical device number 07h biu unused 08hC2fh na activate 30h biu i/o range check 31h biu unused 32hC3fh na memory base address 0 40h biu bits [23:16] descriptor memory base address 0 41h biu bits [15:08] descriptor memory control 42h biu memory range length 0 43h biu bits [23:16] for descriptor memory range length 0 44h biu bits [25:08] for descriptor unused 45hC5fh na i/o base address 0 60h biu bits [15:08] descriptor i/o base address 0 61h biu bits [07:00] descriptor memory control 62hC6fh biu interrupt request level select 0 70h biu interrupt request type select 0 71h biu unused 72hC73h na dma channel select 0 74h biu unused 75hCffh na amd p r e l i m i n a r y 70 AM79C930 the AM79C930 device maps the resource data regis- ter accesses into 1kC16 of the upper 1 kbytes of the flash memory space so that resource data may be read from the flash memory. byte 0 of the AM79C930 device's resource data is mapped to location 1 fc00h of the flash memory. a maximum of 1kC16 bytes of re- source data is allowed by the AM79C930 design. note that the upper 16 bytes of the flash memory are reserved for use by the firmware and the embedded 80188 core for 80188 core initialization. the upper 16 bytes of the flash memory may not be used to store isa plug and play resource data. mac firmware resources the AM79C930 device contains an embedded 80188 core that can be used to perform the majority of the tasks necessary to implement the mac portion of the ieee 802.11 (draft) standard. the following section describes the resources that are available to the 80188 core and, hence, to firmware written for the embedded 80188. mac (80188 core) memory resources the AM79C930 device contains several resources that are accessible through the 80188 core. these resources in- clude: up to 128kC128 bytes of sram, up to 128 kbytes of flash memory, 16 mir registers, 32 tir registers, and 16 bytes of peripheral device space attached to the xce pin. all of the resources that are available to the 80188 core are mapped into 80188 memory space. the lmcs and umcs registers of the 80188 core must be properly programmed to generate ucs and lcs signals in order to take full advantage of all of the resources pro- vided by the AM79C930 device and associated sram, flash and xce devices. (in reality, only ucs is used internally. when an access is performed without the presence of an active ucs signal, then lcs is assumed, and the access is exter- nally directed toward the sram with the sce signal, or internally to the tai register set, or to the external xce device). note that the biu contains at least two separate register spaces. the system interface registers (sir) (space is visible to the system interface, but is not visible to the embedded 80188. the mac interface registers (mir) space is visible to the embedded 80188, but is not vis- ible to the system interface. communication between the device driver and the 80188 core occurs indirectly, as the bits of the mir0 register will affect bits in the general configuration register (sir0) and vice versa. note that a total of 16 bytes of space is reserved for the mir registers, while currently only 10 mir registers are defined. the remaining 6 mir locations are reserved. also note that all 32 tir registers are visible to both the 80188 core and the system interface. AM79C930 80188 memory resources may be mapped using either of two schemes. one scheme makes 256k separate memory locations usable as 128k of flash memory space, 128kC128 bytes of sram, 64 bytes of biu, tai, and xce resources and 64 bytes of reserved space. the other mapping scheme will alias the flash memory into a portion of the sram space. the following text and tables describe each of the mapping schemes. the first mapping scheme (scheme a) places sram, the 32 tir registers, the 16 mir registers, and the 16 xce locations into the lower 128k of memory space. the flash memory is mapped into the upper 128k of memory space. this scheme requires that the lmcs register of the 80188 core be set to 1ff8h. the umcs register of the 80188 core must be set to e038h. also re- quired is that bit 6 of the mir0 register (the mapping se- lect bit) is set to 0. p r e l i m i n a r y amd 71 AM79C930 80188 core memory map using scheme a", lmcs=1ff8h, umcs=e038h, mir0[6]=0 active 80188 address active 80188 AM79C930 size of in memory chip select chip select space physical location of memory 0 0000hC0 03ffh lcs sce 1 kbytes sram memory 0 0000hC0 03ffh 0 0400hC0 041fh lcs none 32 bytes tir 0C31 0 0420hC0 042fh lcs none 16 bytes mir 0C15 0 0430hC0 043fh lcs xce 16 bytes xce locations 0C15 0 0440hC0 047fh lcs none 64 bytes reserved for future useCaccess to these areas is currently undefined 0 0480hC1 ffffh lcs sce 128kC sram memory 0 0480hC1 ffffh 1kC128 bytes 2 0000hCd ffffh none none 768 kbytes undefined e 0000hCf ffffh ucs fce 128 kbytes flash memory 0 0000hC1 ffffh the second mapping scheme (scheme b) places 32k of the sram, the 32 tir registers, the 16 mir registers, and the 16 xce locations into the lowest 32k of memory space, and then maps the upper 96k of flash memory to memory locations 32k through 128k. all 128k of the flash memory is also available at the uppermost 128k memory locations of the 80188 core's address space. this scheme allows the lmcs register of the 80188 core be set to 07f8h or 0ff8h or 1ff8h. the umcs register of the 80188 core must be set to e038h. also required is that bit 6 of the mir0 register (the mapping select bit) is set to 1. note that with mapping scheme b, a maximum of 32kC128 bytes of sram space is available for use. the advantage of mapping scheme b is that when all 80188 firmware can fit into 32k of flash memory space and the sram memory require- ment for the application is less than or equal to 32k, then all 80188 operations occur within a single 64k memory segment. 80188 core memory map using scheme b, lmcs=1ff8h, umcs=e038h, mir0[6]=1 active 80188 address active 80188 AM79C930 size of in memory chip select chip select space physical location of memory 0 0000hC0 03ffh lcs sce 1 kbytes sram memory 0 0000hC0 03ffh 0 0400hC0 041fh lcs none 32 bytes tir 0C31 0 0420hC0 042fh lcs none 16 bytes mir 0C15 0 0430hC0 043fh lcs xce 16 bytes xce locations 0C15 0 0440hC0 047fh lcs none 64 bytes reserved for future useCaccess to these areas is currently undefined 0 0480hC0 7fffh lcs sce 32kC sram memory 0 0480hC1 ffffh 1kC128 bytes 0 8000hC1 ffffh don't care fce 96 kbytes flash memory 0 8000hC1 ffffh 2 0000hCd ffffh none none 768 kbytes undefined e 0000hCf ffffh ucs fce 96 kbytes flash memory 0 0000hC1 ffffh amd p r e l i m i n a r y 72 AM79C930 mac (80188 core) memory resources restrictions some of the AM79C930 device 80188 core's memory locations have predefined uses and, therefore, are not freely available to the firmware. the following table indicates restricted space within the 80188 core memory map of the AM79C930 device: restricted space in the 80188 core memory map using scheme ras or rbs, lmcs=1ff8h, umcs=e038h, mir0[7]=0 or 1 80188 address active 80188 size of in memory chip select space physical location of memory 0 0440hC0 047fh lcs 64 bytes reserved for future use C do not access these locations f fc00hCf ffefh ucs 1kC16 bytes flash memory 1 fc00hC1 ffefh these locations are reserved for use as pcmcia cis or for use as isa plug and play resource data, depending upon the operating mode of the device. these locations must not be used by the 80188 firmware. f fff0hCf ffffh ucs 16 bytes flash memory 1 fff0hC1 ffffh these locations must be used to store the first instructions for the 80188 firmware, since the 80188 core's instruction pointer will point to location f fff0h after a AM79C930 reset. (note that 80188 location f fff0h will appear as 1 fff0h on the memory interface bus, since only 17 address bits are available at the memory interface bus.) total: 1 kbytes mac (80188 core) interrupt channel allocation the tai and biu sections of the AM79C930 device both generate interrupts to the 80188 core. tai generated in- terrupts will always appear on the int0 input of the 80188 core. biu generated interrupts will always appear on the int1 input of the 80188 core. firmware should appropriately recognize the source of each interrupt. interrupt channel allocation in the 80188 core 80188 interrupt channel interrupt source int0 tai int1 biu the interrupt mode used by the 80188 core should be master mode fully nested, since no subunit of the AM79C930 device would respond to 80188 interrupt acknowledge cycles if they occurred. note that when using the master mode fully nested interrupt mode of the 80188 core, no interrupt acknowledge cycles are generated; instead, the interrupt vector for each inter- rupt is generated internally. internally generated interrupt vectors reside in the lower portion of 80188 memory space. tai sourced interrupts may occur due to various condi- tions that are signaled by tai internal state machines. the tir4 and tir5 registers contain most of the bits that signal the various state-machine generated interrupts. the tcr11 location contains a few more interrupt sources. one of the tcr11 interrupt sources is through an external pin, user1/irq12. this allows the user to connect an external interrupt source to the AM79C930 device to allow an interrupt to be generated to the AM79C930 device's internal 80188 core. the biu sourced interrupts are created by software ma- nipulation, i.e., a bit in the driver software's i/o space is written to, and this in turn generates an interrupt to the 80188 microcontroller within the AM79C930 device. in summary, the embedded 80188 controller can be in- terrupted from any of several sources: driver software, internally generated interrupt sources, and from an ex- ternal source through the user1/irq12 pin. mac (80188 core) dma channel allocation the tai section of the AM79C930 device generates dma re- quests to the 80188 core whenever either the transmit fifo (tx fifo) or the receive fifo (rx fifo) of the tai needs servicing. drq0 becomes asserted when- ever the rx fifo is not empty, regardless of the state of the rxs bit of tir16. drq1 becomes asserted when- ever the tx fifo is not full, regardless of the state of the txs bit of tir8. appropriate programming of the dma resources of the 80188 embedded controller is required in order to insure proper response to these requests. for example, when no tx operation is desired, then the dma controller for drq1 should be disabled. note that the use of the 80188 controller's dma re- sources is not required for any given AM79C930-based implementation, since both the rx fifo and the tx fifo are directly accessible as registers. that is, it is possible to use 80188 mov instructions to load tx data into the tx fifo. the tx fifo may be loaded by writing p r e l i m i n a r y amd 73 AM79C930 to tir10. it is also possible to use 80188 mov instruc- tions to unload rx data from the rx fifo. the rx fifo may be unloaded by reading from tir18. dma channel allocation in the 80188 core 80188 dma channel dma request source drq0 tai rx fifo not empty drq1 tai tx fifo not full loopback operation the AM79C930 device contains a loopback mode that is invoked by writing a 1 to the loopb bit of tcr3[7]. when loopb is set to a 1, then the AM79C930 device will perform an internal loopback of all transmissions. the data path transmitted will move out of the tx fifo and be serialized. use of shared resources can be controlled by the order of writing to the txs and rxs bits of tir8 and tir16, respectively. the bit (of txs and rxs) that is set last will determine the owner of the sfd detection logic shared resource. led support two pins are provided with the necessary drive capabil- ity to directly drive a standard indicator led. the output value for these pins is directly programmable through tir register bits that are accessible to both the 80188 embedded core through the memory interface and to the driver software through the system interface. these two pins are also programmable as inputs so that alter- native functionality may be defined for these pins. reset methods there are multiple reset conditions that can be applied to the AM79C930 device. each of the reset con- ditions and its effect on the device are indicated in the following sections. reset pin there is a single reset input to the AM79C930 device. when the reset pin is asserted for the specified mini- mum time and then the reset pin is deasserted, gen- erally speaking, all major state machines in the AM79C930 device and all registers in the AM79C930 device are reset to their default values, with the excep- tions noted below. the following registers and state machines are reset to their default values by assertion of the reset pin: (note that some register locations' default values are undefined): all sir registers, except sir2[7:0] and sir3[6:0], which are unaffected. all mir registers. all tir registers. all tcr registers. all tai state machines. all pcmcia registers. all isa pnp registers. the isa pnp state machine is returned to its idle state. the 80188 controller is held in reset as long as the reset pin is held asserted. the sleep state machine is returned to its idle state (i.e., awake). the memory bus arbitration state machine is re- turned to its idle state. the biu will be reset to an inactive state, such that all tri-stateable outputs will be put into a high-impedance state. the internal slave state machine will revert to the idle state; any slave operation that was in progress at the time of the reset operation will be abruptly discon- tinued. the biu will recognize a new slave access from the host beginning four clkin clocks of the deassertion of the reset pin. the embedded 80188 controller will be reset by the as- sertion of the reset pin, provided that the minimum pulse width requirement for the reset signal is met. any tx or rx operation that was in progress at the tai at the time of the reset assertion will be discontinued abruptly. all rx and tx fifo data will remain in the fifos. rx and tx fifos can only be cleared by asser- tion of the rxfr and txfr bits of tir16 and tir8. tai unit will not resume tx and rx operations until the 80188 core instructs it to do so. swreset (sir0[7]) the swreset bit of sir0[7] can be used to reset the system interface section of the AM79C930 device. when the swreset bit is asserted, then the biu sec- tion of the AM79C930 device will be reset, including the arbitration state machine that translates 80188 cycles into memory bus cycles. the following registers and state machines are reset to their default values by assertion of the swreset bit of sir0[7]: (note that some register locations' default values are undefined): all sir registers, except sir0[7] and all of sir2[7:0] and sir3[6:0] which are unaffected. all mir registers. amd p r e l i m i n a r y 74 AM79C930 the sleep state machine is returned to its idle state (i.e., awake). the memory bus arbitration state machine is re- turned to its idle state. the following registers and state machines which are unaffected by assertion of the swreset bit of sir0[7]: sir0[7] and all of sir2[7:0] and sir3[6:0] are unaf- fected by swreset. tir registers are unaffected by swreset. tcr registers are unaffected by swreset. tai state machines are unaffected by swreset. the 80188 controller is unaffected by swreset. pcmcia registers are unaffected by swreset. isa pnp registers are unaffected by swreset. the isa pnp state machine is unaffected by swreset. it is generally recommended that the swreset bit of sir0[7] should not be set to a 1 unless the coreset bit of sir0[6] has first been set to a 1. this recommendation is to insure that the memory bus arbi- tration state machine is not reset while the 80188 em- bedded controller is executing an access. the proper sequence for using the swreset bit should be: 1. set the coreset bit sir0[6] to a 1. 2. set the swreset bit sir0[7] to a 1. 3. reset the swreset bit sir0[7] to a 0. 4. reset the coreset bit sir0[6] to a 0. an option to this procedure is to first insure that the 80188 controller is in the halt state before the swreset bit is asserted. however, note that the flashwait and sramwait values are reset by swreset; therefore, if 80188 operations are resumed after the swreset has been performed, the perform- ance of the 80188 may be affected. the user may decide not to follow these recommenda- tions, but in such a case, it should be recognized that the 80188 may suffer from unpredictable behavior as a result. coreset (sir0[6]) the coreset bit of sir0[6] can be used to reset the embedded controller and tai sections of the AM79C930 device, along with a few locations in the mir register space. when the coreset bit is asserted, then the 80188 section of the AM79C930 device will be placed into reset, with behavior identical to that of a standalone 80188 controller having its reset pin as- serted. tai section of the AM79C930 device will also be- come reset with all registers returning to their default states, as will a few bits in the mir register set. the following is a complete list of registers and state ma- chines that will become reset to default values with the assertion of the coreset bit of sir0[6]: (note that some register locations' default values are undefined): all tir registers. all tcr registers. mir8[1:0] are reset to 11b. mir9[5:4] are reset to 11b. all tai state machines are reset by the assertion of coreset. the 80188 controller is held in reset as long as the coreset bit is held at a 1 level. the following registers and state machines are unaffected by assertion of the coreset bit of sir0[6]: the isa pnp state machine is unaffected by coreset. the sleep state machine is unaffected by coreset. the memory bus arbitration state machine is unaf- fected by coreset. pcmcia cor sreset the pcmcia configuration option register contains a reset bit in location [7] which is labeled sreset. when sreset is asserted, the entire AM79C930 device will become reset as though the reset pin had been as- serted, except that the asynchronous logic which is used to perform pcmcia register accesses is not reset. the following is a complete list of registers and state ma- chines that will become reset to default values with the assertion of the cor sreset bit of pcmcia cor[7]: (note that some register locations' default values are undefined): all pcmcia registers, except cor[7]. all mir registers. all sir registers, except sir0[7], sir2[7:0], and sir3[6:0]. the memory bus arbitration state machine is re- turned to its idle state. p r e l i m i n a r y amd 75 AM79C930 the sleep state machine is returned to its idle state (i.e., awake). the following registers and state machines are unaffected by assertion of the pcmcia cor sreset bit of cor[7]: all tir registers are unaffected by cor sreset. all tcr registers are unaffected by cor sreset. all tai state machines are unaffected by cor sreset. the 80188 controller is unaffected by cor sreset. it is generally recommended that the sreset bit of cor[7] should not be set to a 1 unless the coreset bit of sir0[6] has first been set to a 1. this recommen- dation is to insure that the memory bus arbitration state machine is not reset while the 80188 embedded control- ler is executing an access. the proper sequence for us- ing the cor sreset bit should be: 1. set the coreset bit sir0[6] to a 1. 2. set the cor sreset bit pcmcia cor[7] to a 1. 3. reset the cor sreset bit pcmcia cor[7] to a 0. 4. reset the coreset bit sir0[6] to a 0. an option to this procedure is to first insure that the 80188 controller is in the halt state before the cor sreset bit is asserted. note however, that the flashwait and sramwait values are reset by cor sreset; therefore, if 80188 operations are re- sumed after the cor sreset has been performed, the performance of the 80188 may be affected. the user may decide not to follow these recommenda- tions, but in such a case, it should be recognized that the 80188 may suffer from unpredictable behavior as a result. isa pnp reset the isa pnp configuration control register may be used to reset the AM79C930 device. writing the value 111b to bits two through zero of this register (i.e., bits [2:0]) will cause an internal reset pulse to occur within the AM79C930 device). the reset pulse will last for 14 clkin periods. this reset will have the same effect as asserting the reset pin of the AM79C930 device, except that, as stated above, the isa pnp reset is limited to a dura- tion of 14 clkin periods. sres (tir0[5]) the sres bit of tir0[5] can be used to reset the tai section of the AM79C930 device. when the sres bit is asserted, then the tai section of the AM79C930 will be reset. the following registers and state machines are reset to their default values by assertion of the sres bit of tir0[5]: (note that some register locations' default values are undefined) all tir registers, except tir0[7:0] which is unaffected. all tcr registers are reset to default values by sres. all tai state machines are reset to idle states by sres. the following registers and state machines are unaffected by assertion of the sres bit of tir[5]: the sleep state machine is unaffected by sres. the memory bus arbitration state machine is unaf- fected by sres. all sir registers are unaffected by sres. all mir registers are unaffected by sres. the 80188 controller is unaffected by sres. pcmcia registers are unaffected by sres. isa pnp registers are unaffected by sres. the isa pnp state machine is unaffected by sres. register descriptions the AM79C930 device has five distinct areas of register storage: system interface register (sir), mac inter- face register (mir), transceiver attachment interface unit register (tir), transceiver attachment interface uniit configuration register (tcr), and the pcmcia (or isa plug and play) register sets. the sir space contains eight registers which are used by the host driver to control AM79C930 device opera- tions and to collect status, namely, the general configu- ration register and the bank switching select register. the local memory address and local memory data registers may be used instead of system-memory- mapped transfers to sram and flash locations in order to eliminate the need for system memory space alloca- tion. these registers are only accessible at the system interface; they are inaccessible from the 80188 core. amd p r e l i m i n a r y 76 AM79C930 the mir space contains 16 registers which are used by the firmware to control allow communication between the firmware (mac layer) and the device driver. this register set also contains the power down registers. these registers are only accessible through the 80188 core; they are inaccessible from the system interface. the tir space contains 32 registers which are used by the 80188 core to control the AM79C930 device's tai unit, to collect tai status, and to transfer data to and from the tai. these registers are accessible from both the system interface and the 80188 core. the tcr space contains 32 registers which are used by the 80188 core to define the functionality of the AM79C930 device's tai unit. these registers are indi- rectly accessible from both the system interface and the 80188 core through an address and data port that are part of the tir set of registers. the pcmcia register set consists of two card configu- ration registers (ccr) and the configuration informa- tion space (cis). full support of the pcmcia standard (version 2.1) is facilitated through these registers. the ccr space is only accessible through the system inter- face. the cis space is accessible from both the system interface and from the 80188 core, although the 80188 core should never need to access the cis. the isa plug and play register set consists of three ba- sic registers which allow an indirect access to an addi- tional 19 plug and play configuration registers plus a double indirect access to 1kC16 bytes of plug and play resource data space. the plug and play register space is only accessible through the system interface, except that the resource data space is also mapped into a por- tion of the 80188 core memory space. note that all register locations are defined to be 8 bits in width. some register bits indicate the value pin for their de- fault reset value. such register bits have a pin as an op- tional data source and such pins are by default defined as inputs; hence, the register bit value of pin indicates that the default register bit value depends upon the value of a pin and is therefore system dependent. some register bits indicate the value C for their default reset value. such register bits have an undefined default value, even though repeated read accesses may yield a consistent result for some bit locations thus marked. amd reserves the right to modify the behavior of these bits at any time in the future (such as in a revision of this device) and, therefore, all values read from these loca- tions should be regarded as unknown until such time as a use has been assigned to them. note also that all such bits have a write value that must be used when write accesses to other bit locations in the register occur. this write value is usually 0. users must strictly obey prescribed write values to avoid future software incompatibility problems. system interface registers (sir space) the sir space contains eight registers which are used by the host driver to control AM79C930 device opera- tions and to collect status, namely, the general configu- ration register and the bank switching select register. the local memory address and local memory data registers may be used instead of system-memory- mapped transfers to sram locations in order to elimi- nate the need for system memory space allocation. these registers are only accessible at the system inter- face; they are inaccessible from the 80188 core. p r e l i m i n a r y amd 77 AM79C930 sir0: general configuration register (gcr) this register is used to control general functions related to the AM79C930, particularly interrupts to and from the 80188 core and power down functions. bit name reset value description 7 swreset 0 software reset. when swreset is set to a 1, the biu will be reset, with the exception of the swreset bit and the software reset bit in the pcmcia card configuration register. the 80188 embedded controller will not be reset. tai will not be reset. swreset is unaffected by the reset bit of the pcmcia configu- ration option register. 6 coreset 0 core reset. when coreset is set to a 1, the 80188 embedded controller and the tai are held in reset. in addition, the flashwait and sramwait fields of mir8 and mir9 are set to their default states of 11b the reset to the 80188 core and the tai remains active as long as coreset has the value 1. during the reset time, the AM79C930 memory interface bus is directly acces- sible through the system interface. 5 dispwdn 0 disable power down mode. when dispwdn is set to a 1, the AM79C930 device will be prevented from entering the power down mode. if the AM79C930 device is already in the power down mode when dispwdn notes a transition from 0 to 1, then the power down mode will be exited within three clkin periods. 4 ecwait 0 embedded controller wait mode. when ecwait is set to 1, the rdy input to the 80188 core will be held deasserted forcing the 80188 core into a wait state. at the same time, the system inter- face side of the biu will be placed into direct access mode, such that system interface access cycles will have direct access to the AM79C930 memory interface. when ecwait is reset to a 0, the rdy line to the 80188 core will be reasserted, the 80188 core will resume operation and system interface direct access mode will cease. ecwait also functions to determine the source of interrupts to the system (through the system interface interrupt pin(s)) as follows: ecwait source of interrupts (sir0[4]) sent to system 0 mir0[2] (note that this bit is set by 80188 firmware) 1 tai interrupt 3 ecint 0 embedded controller interrupt. ecint indicates that an interrupt for the system has been generated by either the 80188 core or the tai. only one interrupt source is operable at one time. the oper- able interrupt source is determined by the setting of the 80188 wait mode bit (sir0[4]). this bit will stay set until the driver soft- ware clears the interrupt by writing a 1 to this bit. amd p r e l i m i n a r y 78 AM79C930 2 int2ec 0 interrupt to embedded controller. when int2ec is set to a 1, an interrupt is sent to the 80188 core. int2ec will stay set at 1 until the 80188 core clears this bit by writing a 1 to bit 3 of the mir0 register. writing a 0 to int2ec will have no effect on the value of int2ec. 1 enecint 0 enable embedded controller interrupts. when set to 1, enables 80188 core-generated interrupts to be passed to the biu, where they will appear as interrupts on the ecint bit of sir0 and also on the system interface interrupt pin. when set to 0, no 80188 core- generated interrupts will be passed to the biu. 0 dam 0 direct access mode. dam is a read-only bit that indicates that the 80188 embedded controller has set the sida bit of mir0 (bit 7), thereby giving the system interface direct accessibility to the mem- ory interface of the AM79C930 device. the 80188 embedded con- troller should only give such access to the system interface when the 80188 follows such action with a halt instruction, otherwise 80188 accesses to the memory interface may interfere with the di- rect access given to the system interface. this mode can be re- leased if the system interface interrupts the 80188. an 80188 interrupt will cause the 80188 to exit the halt state and will allow the 80188 to reset the sida bit to 0. the value of the dam bit is the same as the value of the sida bit of mir0 (bit 7). sir1: bank switching select register (bss) this register contains bank select bits for various AM79C930 resources and other control bits. bit name reset value description 7 ecatr 0 embedded controller ale test read. contains latched ale value from the 80188 core. writing a 0 will clear this bit. whenever the 80188 core ale signal becomes active (1), then this bit will become 1 and will stay 1 until either it is written as a 0 or a reset occurs. 6 reserved C read only as a 0. 5 fs 0 flash select. when fs is set to 1, common memory accesses across the host bus will be made to the flash memory, not sram. when fs is reset to 0, the host accesses are directed to the sram. 4:3 mbs 00 memory bank select. these two bits act as AM79C930 memory in- terface bus address bits ma[16:15] during system interface ac- cesses to flash and sram. 2 eiow 0 expand i/o window. when eiow is reset to 0, the tai can only be accessed through system interface addresses i/o offsets 0008h through 000fh and the tai bank select bits must be used to access the full set of tir registers. when eiow is set to 1, the tai address space is mapped to system interface addresses i/o offsets 0008h through 0027h. eiow is always 0 when the AM79C930 device has been set to the isa plug and play mode of operation. eiow is not writeable when the AM79C930 device has been set to the isa plug and play mode of operation. 1:0 tbs 00 tai bank select. when the eiow bit is set to 0, then the tbs bits will act as AM79C930 memory interface bus address bits ma[4:3] during system interface accesses to the tir registers. p r e l i m i n a r y amd 79 AM79C930 sir2: local memory address register [7:0] (lma) this register is the beginning address on the local bus for system interface i/o transfers that are made to the i/o data port. this register automatically increments by 1 following each read or write operation of any section of the i/o data port. (ma[16:15] will be given the values of bss[4:3] C memory bank select bits.) bit name reset value description 7:0 lma[7:0] C these 8 bits act as AM79C930 memory interface bus address bits ma[7:0] during system interface accesses to flash and sram whenever any section of the i/o data port is read or written. the lma[14:0] value is automatically incremented by r1s after any section of the i/o data port is read or written. note that these bits are unaffected by any reset operation. sir3: local memory address register [14:8] (lma) this register is the beginning address on the local bus for system interface i/o transfers that are made to the i/o data port. this register automatically increments by 1 following each read or write operation of any of the i/o data ports in which the lma [7:0] register produces a carry out from bit lma[7]. bit name reset value description 7 isapwrdwn 0 requests the 80188 to enter power down mode if the device is op- erating in the isa plug and play mode. if already in power down mode, this bit will indicate 1. if written with a 0 while in power down mode, power down mode is exited. when written with a 1, value read will remain 0 until the device actually enters the power down mode. when written with a 1, the pwrdwn bit generates an inter- rupt to the 80188, requesting that the 80188 core place the AM79C930 device into the power down state. the interrupt is sig- naled in mir0, bit 5. the pwrdwn bit of sir3 is identical in func- tion to the pcmcia card configuration and status register's power down bit, but this bit is only functional when the isa plug and play mode has been selected. this bit is reserved and should be written as 0 when the pcmcia mode of operation has been selected. reads of this bit produce undefined data when in pcmcia mode. 6:0 lma[14:8] C these seven bits act as AM79C930 memory interface bus address bits ma[14:8] during system interface accesses to flash and sram whenever any section of the i/o data port is read or written. the lma[14:0] value is automatically incremented by 1 after any of the i/o data ports is read or written. (note that ma[16:15] will be given the values of sir1[4:3] C memory bank select bits.) note that these bits are unaffected by any reset operation. sir4: i/o data port a (iodpa) this register directly accesses the AM79C930 memory interface data bus at the memory interface bus address specified by the current value of the lma registers and the sir1[5:3] bits. each read or write operation of any of the i/o data ports causes an increment of 1 to the lsb of the lma. all four i/o data ports will use the same lma and sir1[5:3] values. that is, each i/o data port is equivalent to the others, except for their location in sys- tem i/o space. different i/o data ports do not imply a built in offset of lma values. bit name reset value description 7:0 iodpa[7:0] C these eight bits act as AM79C930 memory interface bus data bits md[7:0] during system interface accesses to flash and sram whenever any section of the i/o data port is read or written. amd p r e l i m i n a r y 80 AM79C930 sir5: i/o data port b (iodpb) this register is a system interface i/o address alias of i/o data port a. bit name reset value description 7:0 iodpb[7:0] C aliased to i/o data port a. sir6: i/o data port c (iodpc) this register is a system interface i/o address alias of i/o data port a. bit name reset value description 7:0 iodpc[7:0] C aliased to i/o data port a. sir7: i/o data port d (iodpd) this register is a system interface i/o address alias of i/o data port a. bit name reset value description 7:0 iodpd[7:0] C aliased to i/o data port a. mac interface registers (mir space) the mac interface unit register (mir) space contains 16 registers which are used by the firmware to allow communication between the firmware (mac layer) and the device driver. this register set also contains the power down registers. these registers are only accessi- ble through the 80188 core; they are inaccessible from the system interface. mir0: processor interface register (pir) this register is used to communicate to and from the driver at the system interface. bit name reset value description 7 sida 0 system interface direct access. when sida is set to 1, then the system interface side of the biu is in direct memory access mode, such that system interface access cycles will have direct access to the AM79C930 memory interface. this mode should only be in- voked if the 80188 will be placed into halt mode by an appropriate instruction within the 80188 firmware during the time that sida is set to 1. when sida is reset to 0, then system interface accesses to the AM79C930 memory interface will be translated by the internal biu arbitration state machine. 6 ecmrms 0 embedded controller memory resource mapping scheme. when ecmrms is set to 1, the top 96k of flash memory is mapped to 80188 memory locations 8000h to 1ffffh. all of flash memory is still available at the normal locations e0000h to fffffh. when ecmrms is reset to 0, flash memory is mapped only to locations e0000h to fffffh. 5 spdreq 0 system power down request. spdreq will indicate a 1 when the device driver writes a 1 to the pcmcia power down request bit in the pcmcia card configuration and status register or when the device driver writes a 1 to the sir3 isapwrdwn bit. when spdreq is a 1, an interrupt to the 80188 will be generated. spdreq will become cleared when the 80188 core writes a 1 to spdreq. p r e l i m i n a r y amd 81 AM79C930 4 pdc 0 power down command. when pdc is set to 1, the power down cy- cle of the biu power down state machine will begin. pdc will auto- matically clear itself after completion of the power down operation. 3 sysint 0 system interrupt. sysint indicates a 1 after the system issues an interrupt command to the 80188 core by writing to the int2ec bit of the gcr register (sir0). sysint will become cleared to a 0 when the 80188 core writes a 1 to sysint. 2 int2sys 0 interrupt to system. when int2sys is set to a 1, an interrupt is generated to the system, provided that the ecwait bit (sir0[4]0 is set to 0. int2sys will stay set at 1 until the system clears it by writing a 1 to ecint (bit 3 of sir0). writing a 0 to int2sys will have no effect. 1 sysintm 0 system interrupt mask. when sysintm is set to a 1, system-gen- erated interrupts (through the sysint bit of mir0) are allowed to be passed to the 80188. when sysintm is reset to 0, no system-generated interrupts will be passed to the 80188. 0 pwdndn 0 power down done. when power down mode is completed, then pwdndn will automatically become set to 1 and an interrupt to the 80188 core will be generated. the 80188 core may clear the pwdndn bit by first writing a 1 to pwdndn and then writing a 0 to pwdndn. note that pwdndn will read as a 0, after writing a 1 to pwdndn, but a 0 must still be written to pwdndn in order to com- plete the reset operation. if a 0 is not written to pwdndn, then the pwdndn will be permanently held in reset. mir1: power up clock time [3:0] (puct) this register is used to determine the length of time that will be used to allow the clkin buffer circuit to power up and stabilize before the end of the power down cycle. the length of the power up phase will be the value of the puct times 0.5 msec. bit name reset value description 7:4 puct[3:0] 0000b length of the power up stabilization time for the clkin buffer cir- cuitry. the resolution of the power up clock timer is in increments of 16x (period of pmx). the nominal pmx1/2 crystal value is 32.768 khz, resulting in a resolution of 16 x 31.25 m s = 500 m s. 3:0 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. mir2: power down length count [7:0] (pdlc) this register is used to determine the length of power down cycles. before execution of the power down se- quence, the 80188 core must load the pdlc counter. upon execution of the power down sequence, the pdlc value will be counted down to zero and the power down cycle will end. bit name reset value description 0 pdlc[7:0] 00h lower 8 bits of the length of the power down cycle counter. the resolution of the power down length counter is in increments of pmx1/2 periods. the nominal pmx1/2 crystal value is 32.768 khz, resulting in a resolution of 31.25 m s. amd p r e l i m i n a r y 82 AM79C930 mir3: power down length count [15:8] (pdlc) this register is used to determine the length of power down cycles. before execution of the power down se- quence, the 80188 core must load the pdlc counter. upon execution of the power down sequence, the pdlc value will be counted down to zero and the power down cycle will end. bit name reset value description 0 pdlc[15:8] 00h middle 8 bits of the length of the power down counter. the resolu- tion of the power down length counter is in increments of pmx1/2 periods. the nominal pmx1/2 crystal value is 32.768 khz, resulting in a resolution of 31.25 m s. mir4: power down length count [22:16] (pdlc) this register is used to determine the length of power down cycles. before execution of the power down se- quence, the 80188 core must load the pdlc counter. upon execution of the power down sequence, the pdlc value will be counted down to zero and the power down cycle will end. bit name reset value description 7 permarest 0 when set to a 1, this bit prevents the normal termination of the power down sequence, such that the pdlc and puct counts are ignored, and the power down mode is only exited when the pcmcia pwrdwn bit is written with a 0, or when the sir0 dispwdn bit is written with a 1. 6:0 pdlc[22:16] 00h upper 7 bits of the length of the power down counter. the resolution of the power down length counter is in increments of pmx1/2 peri- ods. the nominal pmx1/2 crystal value is 32.768 khz, resulting in a resolution of 31.25 m s. mir5: free count [7:0] (fcnt) this register is a read-only register. do not write to this register or unexpected consequences will result. this register gives the value of the lowest byte of the free running count. the free running count is a 24-bit counter that uses the pmx1/2 clock as its basis. the free run- ning count is reset only when the reset pin is asserted. timer resolution is 31.25 m s when pmx1/2 has a fre- quency of 32.768 khz. bit name reset value description 7:0 fcnt[7:0] 00h least significant byte of the free running count. mir6: free count [15:8] (fcnt) this register gives the value of the lowest byte of the free running count. the free running count is a 24-bit counter that uses the 32 khz clock as its basis. the free running count is reset only when the reset pin is asserted. timer resolution is 31.25 m s when pmx1/2 has a frequency of 32.768 khz. bit name reset value description 7:0 fcnt[15:8] 00h middle byte of the free running count. mir7: free count [23:16] (fcnt) this register gives the value of the lowest byte of the free running count. the free running count is a 24-bit counter that uses the 32 khz clock as its basis. the free running count is reset only when the reset pin is asserted. timer resolution is 31.25 m s when pmx1/2 has a frequency of 32.768 khz. bit name reset value description 7:0 fcnt[23:16] 00h most significant byte of the free running count. p r e l i m i n a r y amd 83 AM79C930 mir8: flash wait states this register gives the flash wait states. bit name reset value description 7:4 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. 3 hostallow 1 when this bit equals 1, then the host can access memory; if 0, then the host access is blocked completely 2 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. 1:0 flashwait[1:0] 11b these bits must be set equal to or greater than the number of wait states that are generated internally in the 80188 core as defined by the programming of the r1 and r0 bits of the 80188 umcs register. wait states programmed into flashwait will cause wait states to be inserted into 80188 access to flash and system accesses to flash. each wait state added to a flash access is equivalent to two clkin periods. these bits are interpreted as follows: number of wait states used by arbitration logic for flashwait[1:0] flash accesses 11 3 10 2 01 1 00 0 mir9: tcr mask stschg data this register contains tcr mask, stschg data, and sram wait states. bit name reset value description 7 clkgt20 1 clkin input is greater than 20 mhz. this bit must be set to a 1 by the 80188 code whenever the AM79C930 device is operating in a system that uses a source for the clkin input that is greater than 20 mhz in frequency. this information is needed in order to insure that the tai section of the AM79C930 device is not pushed beyond design limits. specifically, when clkgt20 is set to 1, then the clkin signal is divided by 2 before being fed to the tai section. clkgt20 is also used to calibrate the time delay generated by the hostlongwait counter. specifically, if clkgt20 = 1, then the number of clkin cycles that are counted for a system access wait period is 192 clkin periods; if clkgt20 = 0, then the num- ber of clkin cycles that are counted for a system access wait pe- riod is 96 clkin periods. this time adjustment is needed in order to avoid creating a pcmcia wait signal that exceeds the 12.1 m s limit indicated in the pcmcia specification. if the source for the clkin input is a 20 mhz or slower clock signal, then this bit should remain reset at 0. the clkgt20 bit has an effect on the network data rate. see the table in the data rate bit section in tcr30[2:0]. amd p r e l i m i n a r y 84 AM79C930 6 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. 5:4 sramwait[1:0] 11b these bits must be set equal to or greater than the number of wait states that are generated internally in the 80188 core as defined by the programming of the r1 and r0 bits of the 80188 lmcs register. wait states programmed into sramwait will cause wait states to be inserted into 80188 access to sram and system accesses to sram. each wait state added to an sram access is equivalent to two clkin periods. these bits are interpreted as follows. number of wait states used by arbitration logic for sramwait[1:0] sram 11 3 10 2 01 1 00 0 3 hostlongwait 0 when hostlongwait is set to a 1, 96, or 192 clkin periods (depending upon the setting of the clkgt20 bit of mir9) of ready delay are added to all system access cycles that are di- rected to flash, sram and tai registers. (note that accesses to pcmcia registers, sir registers and isa pnp register are unaf- fected.) this delay is nominally 4.8 m s when clkin = 20 mhz and clkgt20 is set to 0, and nominally 4.8 m s when clkin = 40 mhz and clkgt20 is set to 1. when hostlongwait is set to a 0, all host (system) access cy- cles will be delayed according to their position in the arbitration queue, where the only other master competing is the 80188 core and the requesting device has priority over the current master (i.e., worst case ready delay with hostlongwait set to 0 is equal to 1 access performed by other master plus the number of wait states for the device being accessed.) system write accesses will be posted and, therefore, may not im- mediately experience the longwait delay. however, the posted ac- cess must internally wait for the longwait before becoming completed and this will cause a subsequent system access to expe- rience the full 4.8 m s wait time plus an additional 4.8 m s wait time for a total of 9.6 m s. note, however, that the average wait time per host cycle in this case will still be 4.8 m s. 2 initdn 0 initialization done. when set to a 0, this bit enables the pull up and pull down devices that are attached to the various multi-function pins. when set to a 1, the pull up and pull down devices are disabled, reducing standby current consumption to the minimum possible level. 1 tcr mask 0 tcr mask. when set to a 1, writes to tcr13, tcr14, and tcr15 are ignored. this bit is provided as a security measure against acci- dental reprogramming of network interface pin function by poorly directed system accesses which could cause output-to-output con- nections to become established. 0 stschgd 0 stschg data. if the stschgfn bit of tcr15 has been set to a 1, and the wakeup bit of the pcmcia ccsr is set to a 1, then this bit may be written with a 1 and writing a 0 to this bit has no effect. if the stschgfn bit of tcr15 has been set to a 1, then stschgd is reset to a 0 automatically whenever the wakeup bit of the p r e l i m i n a r y amd 85 AM79C930 pcmcia ccsr is reset to a 0. if the stschgfn bit of tcr15 has been set to a 0, then the value that is written to this bit will be inverted and driven to the ststchg pin of the AM79C930 device. the value that is read from this bit always represents the inverse of the current value of the ststchg pin of the AM79C930 device. this function is only available in pcmcia mode. the complete control of the function of the stschg /bale pin is described in the multi-function pin section. mir10: reserved this register is reserved. bit name reset value description 7:0 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. mir11: reserved this register is reserved. bit name reset value description 7:0 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. mir12: reserved this register is reserved. bit name reset value description 7:0 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. mir13: reserved this register is reserved. bit name reset value description 7:0 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. mir14: reserved this register is reserved. 7:0 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. mir15: reserved this register is reserved. bit name reset value description 7:0 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. amd p r e l i m i n a r y 86 AM79C930 transceiver attachment interface registers (tir space) the transceiver attachment interface (tai) unit con- tains a total of 64 registers. thirty-two of the registers are directly accessible from the 80188 embedded core and from the system interface through the biu. the other 32 registers are indirectly accessed by first writing an index value into the tcr index register (tir24) and then executing a read or write operation to the tcr data port (tir25). since the indirectly accessible regis- ters are used mostly for tai configuration purposes, this set of registers is labeled tai configuration registers (tcr). the following section describes the directly ac- cessible registers of the tai, or tir. the set of 64 tai registers is intended primarily for use by the 80188 firmware. however, access through the system interface bus to the tai register set is provided to allow for direct access by driver code for diagnostic and other purposes. the exact location of the tir register set as viewed from the system interface will depend upon the choice of mapping scheme as indicated by the expand i/o win- dow bit (bit 2 of the bss register (sir1)). the following tables give the address for each of the directly accessi- ble tirs for each of the system interface modes for each of the two mapping schemes, as well as the address for each register as it appears in the memory map of the 80188 embedded core. p r e l i m i n a r y amd 87 AM79C930 tir mapping with sir1 bit 2 (eiow) set to 0 = normal tir window mode. note that eiow = 0 is the only setting of eiow that is allowed while operating in isa pnp mode. tir uses eight i/o addresses: tir sir1[1:0] isa plug 80188 core register (tai bank pcmcia and play address in number tir register name select) i/o address i/o address memory 0 network control 00 0008h ioba+0008h mem 400h 1 network status 00 0009h ioba+0009h mem 401h 2 serial device 00 000ah ioba+000ah mem 402h 3 fast serial port control 00 000bh ioba+000bh mem 403h 4 interrupt register 1 00 000ch ioba+000ch mem 404h 5 interrupt register 2 00 000dh ioba+000dh mem 405h 6 interrupt mask 1 00 000eh ioba+000eh mem 406h 7 interrupt mask 2 00 000fh ioba+000fh mem 407h 8 transmit control 01 0008h ioba+0008h mem 408h 9 transmit status 01 0009h ioba+0009h mem 409h 10 tx fifo data 01 000ah ioba+000ah mem 40ah 11 transmit sequence control 01 000bh ioba+000bh mem 40bh 12 byte counter lsb 01 000ch ioba+000ch mem 40ch 13 byte counter msb 01 000dh ioba+000dh mem 40dh 14 byte counter limit lsb 01 000eh ioba+000eh mem 40eh 15 byte counter limit msb 01 000fh ioba+000fh mem 40fh 16 receiver control 10 0008h ioba+0008h mem 410h 17 receiver status 10 0009h ioba+0009h mem 411h 18 rx fifo data 10 000ah ioba+000ah mem 412h 19 antenna slot 10 000bh ioba+000bh mem 413h 20 crc32 correct count lsb 10 000ch ioba+000ch mem 414h 21 crc32 correct count msb 10 000dh ioba+000dh mem 415h 22 crc8 correct count lsb 10 000eh ioba+000eh mem 416h 23 crc8 correct count msb 10 000fh ioba+000fh mem 417h 24 configuration index 11 0008h ioba+0008h mem 418h 25 configuration data port 11 0009h ioba+0009h mem 419h 26 antenna diversity & a/d 11 000ah ioba+000ah mem 41ah 27 sar 11 000bh ioba+000bh mem 41bh 28 rssi lower limit 11 000ch ioba+000ch mem 41ch 29 user pin data 11 000dh ioba+000dh mem 41dh 30 dummy register 11 000eh ioba+000eh mem 41eh 31 test register 11 000fh ioba+000fh mem 41fh amd p r e l i m i n a r y 88 AM79C930 tir mapping with sir1 bit 2 (eiow) set to 1 = ex- panded tir window mode. note that the setting eiow = 1 is only allowed while operating in pcmcia mode. tir uses 32 i/o addresses: tir sir1[1:0] 80188 core register (tai bank pcmcia address in number tir register name select) i/o address memory 0 network control xx* 0008h mem 400h 1 network status xx 0009h mem 401h 2 serial device xx 000ah mem 402h 3 fast serial port control xx 000bh mem 403h 4 interrupt register 1 xx 000ch mem 404h 5 interrupt register 2 xx 000dh mem 405h 6 interrupt mask 1 xx 000eh mem 406h 7 interrupt mask 2 xx 000fh mem 407h 8 transmit control xx 0010h mem 408h 9 transmit status xx 0011h mem 409h 10 tx fifo data xx 0012h mem 40ah 11 transmit sequence control xx 0013h mem 40bh 12 byte counter lsb xx 0014h mem 40ch 13 byte counter msb xx 0015h mem 40dh 14 byte counter limit lsb xx 0016h mem 40eh 15 byte counter limit msb xx 0017h mem 40fh 16 receiver control xx 0018h mem 410h 17 receiver status xx 0019h mem 411h 18 rx fifo data xx 001ah mem 412h 19 antenna slot xx 001bh mem 413h 20 crc32 correct count lsb xx 001ch mem 414h 21 crc32 correct count msb xx 001dh mem 415h 22 crc8 correct count lsb xx 001eh mem 416h 23 crc8 correct count msb xx 001fh mem 417h 24 configuration index xx 0020h mem 418h 25 configuration data port xx 0021h mem 419h 26 antenna diversity & a/d xx 0022h mem 41ah 27 sar xx 0023h mem 41bh 28 rssi lower limit xx 0024h mem 41ch 29 user pin data xx 0025h mem 41dh 30 dummy register xx 0026h mem 41eh 31 test register xx 0027h mem 41fh *xx = don't care. p r e l i m i n a r y amd 89 AM79C930 tir0: network control general control for the transceiver device attached to the transceiver interface pins. bit name reset value description 7 lnk pin link led. the inverse of the lnk bit value is driven onto the lnk pin when the lnk pin has been enabled for output. the value read from lnk will always represent the inversion of the current value of the lnk pin. the control of the function of the lnk pin is described in the multi-function pin section. 6 act pin activity led. the inverse of the act bit value is driven onto the act pin when the act pin has been enabled for output. the value read from act will always represent the inversion of the current value of the act pin. the control of the function of the act pin is described in the multi-function pin section. 5 sres 0 tai reset. active high. asserting this bit will reset the tai portion of the AM79C930 device, except for this register (i.e., tir0). 4 sstrb 0 software strobe. this bit is intended for software development use. the value written to this bit will be sent to the test output when the device is programmed for test mode. 3 reserved C reserved. must be written as a 0. reads of these bits produce undefined data. 2 rxp 0 rx power control. the inverse of the rxp bit value is driven onto the rxpe pin when the rxpe pin has been enabled for output. the value read from rxp will always represent the inverted logical sense of the current value of the rxpe pin. the control of the func- tion of the rxpe pin is described in the multi-function pin section. 1 lfpe 0 low frequency power control. the inverse of the lfpe bit value is driven onto the lfpe pin when the lfpe pin has been enabled for output. the value read from lfpe will always represent the inverted logical sense of the current value of the lfpe pin. the control of the func- tion of the lfpe pin is described in the multi-function pin section. 0 hfpe 0 high frequency power control. the inverse of the hfpe bit value is driven onto the hfpe pin when the hfpe pin has been enabled for output. the value read from hfpe will always represent the inverted logical sense of the current value of the hfpe pin. the control of the function of the hfpe pin is described in the multi-function pin section. tir1: network status the tai network status register is a general network status register. bit name reset value description 7 tsto 0 test output. this bit is the result of the test multiplexer. 6C3 reserved C reserved. must be written as a 0. reads of these bits produce undefined data. 2 irq 0 interrupt request. this bit represents the current value of the irq output pin. when irq has the value 1, then an interrupt request is active. amd p r e l i m i n a r y 90 AM79C930 1 rxdrq 0 receive fifo dma request. this bit represents the current value of the rxdrq signal to the drq0 input of the 80188 embedded core. 0 txdrq 1 transmit fifo dma request. this bit represents the current value of the txdrq signal to the drq1 input of the 80188 embedded core. tir2: serial device tai serial device register. this register is used to con- trol the serial device interface. bit name reset value description 7 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. 6C4 sds[3:1] 000b serial device select. each of these bits controls one of the serial device select outputs of the AM79C930. bit values are inverted as they appear at the pins. as an example, writing a 1 to the sds[3] bit will cause the sdsel3 output to be driven to a 0. the value read from sds[x] will always represent the current value of the sdsel[x] pin without inversion. the control of the function of the sdsel[x] pins are found in the multi-function pin section. 3 sdcp 0 serial device clock auto pulse generation. when set to a 1, this bit causes the sdclk pin to become active for the duration of the wr# signal at the 80188 interface of the tai whenever the internal AM79C930 tai chip select has been activated and the memory bus address present is 00010b, with higher order bits of ma as don't care (i.e., a write to tir2 is occurring). the value of the sdclk pin during this strobe period depends upon the setting of the sdc bit. the sdc bit gives the inactive state of the sdclk pin. if sdcp is set to 1, then the sdclk pin is complemented from its inactive state while either the 80188 wr# signal is active with the tai chip select also active. when sdcp is set to 0, then the sdc bit has di- rect control of the sdclk pin. the value of the sdc bit must not be changed when the sdcp bit is set to a 1. to change the value of sdc, first set sdcp to a 0. the complete control of the function of the sdclk pin is described in the multi-function pin section. 2 sdc 0 serial device clock. the sdc bit value is driven onto the sdclk pin when the sdclk pin has been enabled for output. the value of the sdc bit must not be changed when the sdcp bit is set to a 1. to change the value of sdc, first set sdcp to a 0. the value read from sdc will always represent the current value of the sdclk pin. the control of the function of the sdclk pin is de- scribed in the multi-function pin section. 1 sddt 0 serial device data tristate. when sddt is set to 1, the sddata pin of the AM79C930 device is tri-stated. when sddt is set to 0, the sddata pin is driven with the value of the sdd bit. the complete control of the function of the sddata pin is de- scribed in the multi-function pin section. 0 sdd 0 serial device data. the sdd bit value is driven onto the sddata pin when the sddata pin has been enabled for output. p r e l i m i n a r y amd 91 AM79C930 the value read from sdd will always represent the current value of the sddata pin. the complete control of the function of the sddata pin is described in the multi-function pin section. when the fast serial port (tir3) is used, then the value written to sdd will be exclusive or'd (xor) with the data from the fsd bits of tir3 before the fsd bits are sent to the sddata pin. tir3: fast serial port control this register provides a relatively quick write access to the serial port signals of the device (i.e., sdclk and sddata). the sdsel3 - 1 signals must be previously set with an access to the serial port control register (tir2). the sddt bit of tir2 must be set to 0 or the fast write will fail. a write to the tir3 register will initiate the fast serial transfer. a read from this register will not cause any activity at the serial port pins. the clock for the serial port write operation will be created from the clkin signal when the clkgt20 bit of mir9 is set to 0 and from the clkin signal divided by two when the clkgt20 bit of mir9 is set to 1. timing for the fast read operation is as follows: 20138b-8 sddata sdclk ta ta = period of clkin when clkgt20 = 0 ta = (period of clkin) x 2 when clkgt20 = 1 2 x ta ta ta 2 x ta ta ta 2 x ta ta figure 3. serial port fast read timing bit name reset value description 7:5 bcnt[2:0] C byte count. from 1 to 5 bits of the fsd[4:0] data may be sent dur- ing one fast access to the serial port. the value of bcnt[2:0] deter- mines exactly how many bits will be sent for any access. the value bcnt[2:0] = 1 represents a value of one bit to be sent. 4:0 fsd[4:0] C fast serial data[4:0] this is the data that is sent out during the fast serial port access. bit 0 is sent first. fsd bit values are exclusive or'd (xor) with the value written to the sdd bit of tir2[0] before being sent to the sddata pin. tir4: interrupt register 1 the tai interrupt register 1 provides interrupt status in- formation. any interrupt bit may be cleared by writing a 1 to the bit location. writing a 0 to a bit location has no ef- fect on the bit value. when the unmask bit for any interrupt is set to 0, then the bit in the interrupt register may still become set, but no interrupt to the 80188 em- bedded controller will occur. bit name reset value description 7 chbsyc 0 chbsy change of state. indicates that there is a change of state in the cca indication. 6 antsw 0 antenna switch. this bit will become set at the end of each time slot as programmed in the antenna diversity timer register (tcr4) to indicate that the channel tests for this antenna selection have been completed. this bit is reset to 0 when the rxres bit of tir16 is set to 1, or if a 1 is written to antsw. amd p r e l i m i n a r y 92 AM79C930 5 moreint 1 more interrupts. moreint will become set whenever there are interrupt bits set in interrupt register 3 (tcr11). note that moreint bit does not reflect the state of interrupt status bits from interrupt register 2 (tir5). there is an unmask bit for moreint, and there are also individual unmask bits for the interrupts in inter- rupt register 3 (tcr11). 4 txcnt 0 tx count reached. txcnt becomes set to a 1 when the tx byte count limit of tir14 and tir15 has been reached as indicated by the tir12 and tir13 counter. note that reaching the byte count limit will not cause tx operations to automatically cease. tx data transmission ceases only when the tx fifo has become empty. 3 txdone 0 txdone. indicates that the crc has been sent for the current tx frame. if the option for no tx crc has been selected, then txdone will be set to a 1 when the last data bit for the frame has been sent. 2 crcs 0 crc start. crcs will be set to a 1 by the AM79C930 device when the first bit of the crc is being transmitted. if the no tx crc option has been set, then crcs will not become set. 1 sdsnt 0 start of frame delimiter sent during a tx operation. 0 txfbn 1 tx fifo byte needed. indicates that the tx fifo is not full. tir5: interrupt register the tai interrupt register 2 provides interrupt status in- formation. any interrupt bit may be cleared by writing a 1 to the bit location. writing a 0 to a bit location has no ef- fect on the bit value. when the unmask bit for any interrupt is set to 0, then the bit in the interrupt register may still become set, but no interrupt to the 80188 em- bedded controller will occur. bit name reset value description 7 rxcnt 0 rx count reached. rxcnt becomes set to a 1 when the rx byte count limit of tir14 and tir15 has been reached as indicated by the tir12 and tir13 counter. note that reaching the byte count limit will not cause rx operations to automatically cease. rx data reception ceases only when the rx fifo is reset by the 80188 controller. 6 crc8g 0 crc8 good. the crc8 machine has detected a good crc and has latched the byte count that was active at the time that the crc was good. 5 crc32g 0 crc32 good. the crc32 machine has detected a good crc and has latched the byte count that was active at the time that the crc was good. 4 rxfor 0 rx fifo overrun. the rx fifo encountered an overrun condition. 3 rxfba 0 rx fifo byte available. the rx fifo has at least one byte of data available for removal. the status register for the rx fifo indicates the exact number of bytes in the rx fifo. 2 sdf 1 start delimiter found. the sfd has been found, indicating that the receive state machine will now begin placing received bytes into the rx fifo. 1 bcf 0 busy channel found. bcf is set to 1 by the AM79C930 device when a busy channel has been found by the cca logic. that is, whenever chbsy=1, which implies that the channel is busy. 0 aloki 0 antenna lock interrupt. aloki becomes set when the antenna se- lection logic has chosen an antenna based upon the programmed antenna selection criteria. p r e l i m i n a r y amd 93 AM79C930 (generated from the internal signal stop_d, which indicates that an- tenna diversity operation has selected an antenna.) assertion of aloki indicates the cessation of antenna diversity activity so that the incoming network signal can be tracked and decoded by the dpll. aloki will be set to a 1 by the AM79C930 device when the conditions for stopping the antenna diversity switching as set up in the baud detect circuit control registers, tcr17, tcr18, tcr20, tcr21, tcr22, and tcr23, and the rssi limit register tir28, and the cca, and antenna diversity control register tcr28, have been met. tir6: interrupt unmask register 1 interrupt unmask register 1. each bit in this register will unmask the corresponding interrupt of interrupt regis- ter 1 (tir4) when the unmask bit is set to 1. when the unmask bit for any interrupt is set to 0, then the bit in the interrupt register may still become set, but no interrupt to the 80188 embedded controller will occur. bit name reset value description 7 chbsycu 0 chbsy change interrupt unmask. 6 antswu 0 antenna switch interrupt unmask. 5 moreintu 0 moreint interrupt unmask. 4 txcntun 0 tx byte count interrupt unmask. 3 txdone 0 txdone interrupt unmask. 2 crcsu 0 crc start interrupt unmask. 1 sdsntu 0 start of frame delimiter sent interrupt unmask. 0 txfbnu 0 tx fifo byte needed interrupt unmask. tir7: interrupt unmask register 2 interrupt unmask register 2. each bit in this register will unmask the corresponding interrupt of interrupt register 2 (tir5) when the unmask bit is set to 1. when the unmask bit for any interrupt is set to 0, then the bit in the interrupt register may still become set, but no interrupt to the 80188 embedded controller will occur. bit name reset value description 7 rxcntu 0 rx byte count interrupt unmask. 6 crc8gu 0 crc8 good interrupt unmask. 5 crc32gu 0 crc32 good interrupt unmask. 4 rxforu 0 rx fifo overrun interrupt unmask. 3 rxfbau 0 rx fifo byte available interrupt unmask. 2 sdfu 0 start delimiter found interrupt unmask. 1 bcfu 0 busy channel found interrupt unmask. 0 alokiu 0 antenna lock interrupt found interrupt unmask. amd p r e l i m i n a r y 94 AM79C930 tir8: transmit control this register is the transmitter control register. bit name reset value description 7 txres 0 transmit reset. when this bit is set to 1, the internal transmit re- set signal is asserted. when this bit is set to 0, the internal transmit reset signal is deasserted. the transmit fifo is not reset by txres. 6 txfr 0 transmit fifo reset. when this bit is set to 1, the internal transmit fifo reset signal is asserted. when this bit is set to 0, the internal transmit fifo reset signal is deasserted. 5 dma_sel 0 dma select. when this bit is set to 1, the txfifo not_full signal is routed to both of the 80188 dma channels. when this bit is set to 0, the txfifo not_full signal is routed to only dma channel 1 of the 80188. 4 en_tx_crc 0 enable crc-based transmission. when this bit is set to 1, the in- itiation of a transmission will commence when the logical and of the txs bit (tir8, bit 0) and the crc32_good output of the crc32 block becomes true. typically, the en_tx_crc bit and the txs bit are set together during a reception, such that if the re- ception concludes with a correct crc32 indication, then the trans- mit state machine will automatically be started. when this bit is set to 0, initiation of transmission will commence solely on the basis of the setting of the txs bit (tir8, bit 0). 3 rate_sw C rate switch. when this bit is set to 1, the rate of data transmission will automatically change immediately following the transmission of the last bit of the pfl th byte that follows the last bit of the start of frame delimiter, where pfl is defined in tcr3, bits [3:0}. since the pfl field of tcr3 is typically used to demark the phy header from the mac data (and hence, it is used to determine the starting point for mac crc32 calculation), the rate switch will typically oc- cur on the phy/mac boundary. the rate of transmission will change from dr to dr xor 0x1, where dr is the data rate field as defined in tcr30, bits [2:0}. when this bit is set to 0, no rate switch will occur. rx operations are unaffected by this bit. for rate switch- ing on the rx side, an external decode to rx clock and tx data is typically performed. 2C1 tcrc[1:0] 00b transmit crc type. these two bits are used to determine the na- ture of the crc field that is appended to the current frame. these bits must be stable throughout any given transmission. the follow- ing interpretations have been assigned to these bits: tcrc[1:0] transmitted crc 00 no crc is appended 01 crc8 is appended 10 crc32 is appended 11 no crc is appended 0 txs 0 transmit start. when this bit is set to 1, then the transmit state machine begins op- eration. the transmit state machine is edge-sensitive; that is, this bit must be reset to 0 and set again to 1 before a subsequent trans- mission will begin. the transmit busy bit will be set in the transmit status register (tir9) to indicate the state of transmit. resetting this bit to 0 during transmission will not cause the current transmission to be aborted. transmission abort is performed with the txres bit. p r e l i m i n a r y amd 95 AM79C930 tir9: transmit status transmit status register. indicates the current status of the transmit portion of the tai. writes to these bits have no effect. bit name reset value description 7 txcrc 0 transmit crc. txcrc becomes set when the crc is being ap- pended to the end of the transmit frame. txcrc is reset when the transmission of the last bit of the crc is completed. 6 txsdd 0 transmit start delimiter. txsdd becomes set after the start of frame delimiter has been sent. this signal is deasserted when the reset pin is asserted or the coreset bit is set to 1 (sir0), when the txres bit is set to 1 (tir8), or when rxres bit is set to 1 (tir16), or when the rxs bit is set to 1 (tir16), or the sres bit is set to 1 (tir0). if a crc is appended to the frame, then txsdd will be reset after the last bit of the crc is appended to the frame. 5 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. 4C1 txfc[3:0] 8h transmit fifo count. txfc indicates the current count of the num- ber of spaces available in the tx fifo. the tx fifo holds 8 bytes. a txfc value of 8h indicates an empty tx fifo, i.e., 8 spaces are available. a txfc value of 0h indicates a full tx fifo, i.e., 0 spaces are available. 0 txbsy 0 tx busy. this bit is set to 1 by the AM79C930 device when the transmit operation begins and remains set until the transmission has completed. specifically, the txbsy bit will be active whenever the internal o _ tx signal is active as indicated in the tx timing dia- gram found in the AM79C930-based tx power ramp control section. when the txc pin is configured as an input, then the txbsy signal will remain active until both the byte-wide tx fifo and the 16-bit serial fifo have emptied. a write to this bit has no effect. tir10: tx fifo data register this register is the tx fifo data register. this register allows direct access to the tx fifo in the tai. when written, the tx fifo write pointer is automatically incremented. when read, the tx fifo read pointer is automatically incremented. bit name reset value description 7:0 txf[7:0] C transmit fifo data port. when written, data is placed into the sys- tem side of the transmit fifo. when read, data is removed from the network side of the transmit fifo. reads of this register should be for diagnostic purposes only and will not be necessary during nor- mal operation. tx fifo write and read pointers are automatically incremented when writes and reads occur, respectively. amd p r e l i m i n a r y 96 AM79C930 tir11: transmit sequence control this register is the transmit sequence control. the bits in this register determine the function of the transmit sequence signals. bit name reset value description 7 rxcd pin rxc/irq10 pin data. the value that is written to this bit will be driven out to the rxc pin when the rxcen bit of tcr15 has been set to a 1 and the rxcfn bit of tcr28 has been set to a 0. the value that is read from rxcd represents the current value of the rxc/irq10 pin. the control of the function of the rxc/irq10 pin is described in the multi-function pin section. 6 user6d pin user6/irq5 pin data. the value that is written to user6d may be driven out to the user6/irq5 pin, depending upon the values of the user6en bit (tcr15[3]), the user6fn bit (tcr7[6]), the isa pnp registers 70h and 71h, and the operating mode of the AM79C930 device. the value read from user6d will always represent the current value of the user6/irq5 pin. the control of the function of the user6/irq5 pin is described in the multi-function pin section. 5 user5d pin user5/irq4 pin data. the value that is written to user5d may be driven out to the user5/irq4 pin, depending upon the values of the user5en bit (tcr15[2]), the user5fn bit (tcr7[5]), the isa pnp registers 70h and 71h, and the operating mode of the AM79C930 device. the value read from user5d will always represent the current value of the user5/irq4 pin. the control of the function of the user5/irq4 pin is described in the multi-function pin section. 4 llocke pin llocke pin data value. the value that is written to llocke may be driven out to the llocke/sa15 pin, depending upon the values of the llocken bit (tcr14[6]), and the operating mode of the AM79C930 device (i.e., pcmcia or isa). the value read from llocke will always represent the current value of the llocke/sa15 pin. the control of the function of the llocke/sa15 pin is described in the multi-function pin section. 3 rcen 0 register control enable. used to control the functional timing of the txcmd , txmod and txpe pin values as defined in the multi-function pin section. see the multi-function pin section de- scription for each of these pins for more details. 2 txmod 0 txmod pin control. used to control the functional timing of the txcmd , pin value as defined in the multi-function pin section. see the multi-function pin section description for more details. 1 txpe 0 txpe pin control. the txpe bit affects the value of the txpe pin as described in the multi-function pin section. 0 txcmd 0 txcmd and txcmd pin control. the txcmd bit affects the value of the the txcmd and txcmd pins as described in the multi-func- tion pin section. p r e l i m i n a r y amd 97 AM79C930 tir12: byte count register lsb this register is the byte count register lsb. this register contains the lower 8 bits of the 12-bit byte count for receive and transmit messages. this is a working register; access by software is not needed for normal operation. bit name reset value description 7:0 bc[7:0] 00h byte count. lower eight bits of current byte count for both transmit and receive operations. during transmit operations, the byte count reflects the number of bytes that have been transmitted following the transmission of the start of frame delimiter. crc is not in- cluded in this count for tx. during receive operations, the byte count reflects the number of bytes that have been written into the rx fifo. this total excludes preamble and start of frame delimiter bytes, but includes any phy field and crc bytes. write accesses to this register from the software will cause unexpected results. tir13: byte count register msb this register is the byte count register msb. this regis- ter contains the upper 4 bits of the 12-bit byte count for receive and transmit messages. this is a working register; access by software is not needed for normal operation. bit name reset value description 7C4 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. 3C0 bc[11:8] 0h byte count. upper 4 bits of current byte count for both transmit and receive operations. during transmit operations, the byte count re- flects the number of bytes that have been transmitted following the transmission of the start of frame delimiter. crc is not included in this count for tx. during receive operations, the byte count reflects the number of bytes that have been written into the rx fifo. this total excludes preamble and start of frame delimiter bytes, but in- cludes any phy field and crc bytes. write accesses to this regis- ter from the software will cause unexpected results. tir14: byte count limit lsb this register is the byte count limit lsb register. bit name reset value description 7C0 bclt[7:0] 00h byte count limit. lower eight bits of byte count limit for both trans- mit and receive operations, depending upon which operation is currently occurring. during transmit operations, when the byte count limit is reached, an interrupt to the 80188 controller will be generated if the txbcnt interrupt has been unmasked. during tx, the byte counter counts all bytes beginning with the first byte after the sfd field has been detected and does not count the crc bytes appended to the tx frame. during rx, when the byte count limit is reached, an interrupt to the 80188 controller will be generated if the rxbcnt interrupt has been unmasked. during rx, the byte counter counts all bytes that follow the start of frame delimiter. byte count limit has no effect on state machine or fifo operations. amd p r e l i m i n a r y 98 AM79C930 tir15: byte count limit msb this register is the byte count limit msb register. bit name reset value description 7C4 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. 3C0 bclt[11:8] 0h byte count limit. upper 4 bits of byte count limit for both transmit and receive operations, depending upon which operation is cur- rently occurring. during transmit operations, when the byte count limit is reached, an interrupt to the 80188 controller will be gener- ated if the txbcnt interrupt has been unmasked. during tx, the byte counter counts all bytes beginning with the first byte after the sfd field has been detected and does not count the crc bytes ap- pended to the tx frame. during rx, when the byte count limit is reached, an interrupt to the 80188 controller will be generated if the rxbcnt interrupt has been unmasked. during rx, the byte counter counts all bytes that follow the start of frame delimiter. byte count limit has no effect on state machine or fifo operations. tir16: receiver control this register is the receiver control register. this regis- ter allows basic control of the receive function. bit name reset value description 7 rxres 0 receive reset. when this bit is set to 1, the internal receive reset signal is asserted. when this bit is set to 0, the internal receive re- set signal is deasserted. the receive fifo is not reset by rxres. 6 rxfr 0 receive fifo reset. when this bit is set to 1, the internal receive fifo reset signal is asserted. when this bit is set to 0, the internal receive fifo reset signal is deasserted. 5C1 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. 0 rxs 0 receive start. when this bit is set to 1, then the receive state ma- chine begins operation. drq indications based upon rx fifo status are independent of the value of this bit. the receive state machine is edge-sensitive, that is, this bit must be reset to 0 and set again to 1 before a subsequent reception will begin. the receive busy bit will be set in the receive status register (tir17) to indicate the state of reception. resetting this bit to 0 during a reception will not cause the current reception to be aborted. receive abort is per- formed with the rxres bit. tir17: receive status register this register is the rx status register. indicates the cur- rent status of the receive portion of the tai. bit name reset value description 7 crc32 0 crc32 good. the crc32 machine has detected a good crc and has latched the byte count that was active at the time that the crc was good. 6 crc8 0 crc8 good. the crc8 machine has detected a good crc and has latched the byte count that was active at the time that the crc was good. p r e l i m i n a r y amd 99 AM79C930 5 rxfor 0 receive fifo overrun. this bit is set whenever the rx fifo expe- riences an overrun. this bit is cleared by resetting the rx fifo. 4C1 rxfc[3:0] 0 receive fifo count. these bits indicate the current count of the number of bytes contained in the rx fifo. the rx fifo holds 15 bytes. an rxfc value of 0h indicates an empty rx fifo. an rxfc value of fh indicates a full rx fifo. 0 rxbsy 0 rx busy. this bit is set to 1 by the AM79C930 device when the rxs bit of tir16 is set to a one, and remains set until the rxres bit of tir16 is set to a one, or until any other global reset is activated (e.g., reset pin of AM79C930 asserted or the coreset bit of sir0 is set). tir18: rx fifo data register this register is the rx fifo data register. this register allows direct access to the rx fifo in the tai. when read, the rx fifo read pointer is automatically incremented. when written, the rx fifo write pointer is automatically incremented. bit name reset value description 7:0 rxf[7:0] C receive fifo data port. when read, data is removed from the sys- tem side of the receive fifo. when written, data is placed into the network side of the receive fifo. writes to this register should be for diagnostic purposes only and will not be necessary during nor- mal operation. rx fifo write and read pointers are automatically incremented when writes and reads occur, respectively. tir19: reserved this register is reserved. bit name reset value description 7C0 reserved C reserved. must be written as a 0. reads of these bits produce undefined data. tir20: crc32 correct byte count lsb this register is the crc32 correct byte count lsb register. bit name reset value description 7C0 c32c[7:0] C crc32 correct count. the value in this register indicates the lower 8 bits of the 12-bit byte position when the crc32 value was last cor- rect. crc32 value 001h corresponds to the first byte of the received message following the start of frame delimiter. if the value in this register (and tir21) does not match the length value indicated in the frame header (plus overhead for phy and mac headers and crc) for frames that employ 32-bit crc values, then the frame should be rejected by the mac firmware. note that all bytes begin- ning with the first byte following the start of frame delimiter and in- cluding the crc bytes are included in the crc32 correct count value, but the bytes that are included in the crc32 calculation are dependent upon the setting of the pfl bits of tcr3. amd p r e l i m i n a r y 100 AM79C930 tir21: crc32 correct byte count msb this register is the crc32 correct byte count msb register. bit name reset value description 7C4 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. 3C0 c32c[11:8] C crc32 correct count. the value in this register indicates the upper 4 bits of the 12-bit byte position when the crc32 value was last cor- rect. crc32 value 001h corresponds to the first byte of the received message following the start of frame delimiter. if the value in this register (and tir20) does not match the length value indicated in the frame header (plus overhead for phy and mac headers and crc) for frames that employ 32-bit crc values, then the frame should be rejected by the mac firmware. note that all bytes begin- ning with the first byte following the start of frame delimiter and in- cluding the crc bytes are included in the crc32 correct count value, but the bytes that are included in the crc32 calculation are dependent upon the setting of the pfl bits of tcr3. tir22: crc8 correct byte count lsb this register is the crc8 correct byte count lsb register. bit name reset value description 7C0 c32c[7:0] C crc8 correct count. the value in this register indicates the lower 8 bits of the 12-bit byte position when the crc8 value was last cor- rect. crc8 value 001h corresponds to the first byte of the received message following the start of frame delimiter. if the value in this register (and tir22) does not match the length value indicated in the frame header (plus overhead for phy and mac headers and crc) for frames that employ 8-bit crc values, then the frame should be rejected by the mac firmware. note that all bytes begin- ning with the first byte following the start of frame delimiter and in- cluding the crc bytes are included in the crc8 correct count value, but the bytes that are included in the crc8 calculation are dependent upon the setting of the pfl bits of tcr3. tir23: crc8 correct byte count msb this register is the crc8 correct byte count msb register . bit name reset value description 7C4 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. 3C0 c8c[11:8] C crc8 correct count. the value in this register indicates the upper 4 of the 12-bit byte position when the crc8 value was last correct. crc8 value 001h corresponds to the first byte of the received mes- sage following the start of frame delimiter. if the value in this regis- ter (and tir22) does not match the length value indicated in the frame header (plus overhead for phy and mac headers and crc) for frames that employ 8-bit crc values, then the frame should be rejected by the mac firmware. note that all bytes beginning with the first byte following the start of frame delimiter and including the crc bytes are included in the crc8 correct count value, but the bytes that are included in the crc8 calculation are dependent upon the setting of the pfl bits of tcr3. p r e l i m i n a r y amd 101 AM79C930 tir24: tcr index register this register is the tcr index register. this register is used as an address into indirect tai register space. the value in the tcr index register is used as an address that points at one of 64 registers that are accessed through the tcr data port. bit name reset value description 7:6 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. 5:0 tcri[5:0] 00h tcr index value. the value in the tcr index register is used as an address that points at one of 64 registers that are accessed through the tcr data port. tir25: configuration data port this register is the configuration data port register. this register is used as the data port allowing access to 64 indirectly accessed registers. the register that is accessed through the configuration data port is deter- mined by the current setting of the configuration index register. bit name reset value description 7C0 cd[7:0] C configuration register data. this register is used as the data port allowing access to 64 indirectly accessed registers. the register that is accessed through the configuration data port is determined by the current setting of the configuration index register. tir26: antenna diversity and a/d control this register is the antenna diversity and a/d control register. bit name reset value description 7 chbsy 0 channel busy. the AM79C930 device will set this bit to a 1 when the clear channel assessment logic determines that a carrier is pre- sent. the AM79C930 device will set this bit to a 0 when the clear channel assessment logic determines that a carrier is not present. writes by firmware will have no effect on this bit. 6 antlok 0 antenna selection locked. the AM79C930 device will set antlok to a 1 when it has determined that criteria for antenna se- lection have been passed. the AM79C930 device will set antlok to a 0 when the rxs bit of tir16 is set 1. 5 antslt 0 antenna selection. this bit gives the current value of the antslt pin, whether determined by register bit programming or internal an- tenna selection logic. this bit is read only. 4 ants 0 antenna switch. if antsen is set to 1, then the software may di- rectly control the value of the antslt and antslt pins with this bit. if antsen is set to 0, then writes to this bit will have no effect on the value of the antslt and antslt pins. note: antenna diversity is disabled with the antsen bit (bit 3 of tir26). 3 antsen 0 antenna switch enable. antsen and antsltlfn (tcr30[7]) are combined with the pcmcia pin setting to determine the func- tionality of the antslt and antslt pins. the complete control of the function of the antslt and antslt pins are described in the multi-function pin section. amd p r e l i m i n a r y 102 AM79C930 2 adda 0 a/d d/a mode. adda is used with enext (tcr25[6]), ensar (tcr25[5]), and uxa2dst (tcr25[7]) to determine the mode of operation of the a/d portion of the AM79C930 device according to the following table: adda enext ensar uxa2dst a/d tir26[2] tcr25[6] tcr25[5] tcr25[7] mode 0 0 0 0 internal_a 0 0 0 1 reserved 0 0 1 0 internal_b 0 0 1 1 internal_c 0 1 0 x external 0 1 1 x reserved 1 x 0 x reserved 1 x 1 x d/a mode for a complete description of the operation of each of the above modes, see the rssi a/d subsection of the tai section. 1 srcs 0 a/d source select. when srcs is set to 0, then adin1 is the input to the a/d converter for internal a/d modes. when srcs is set to 1, then adin2 is the input to the a/d converter for internal a/d modes. srcs has no effect when external or d/a mode has been selected. 0 strtc 0 start conversion. whenever a 1 is written to strtc (i.e., even if the bit value is already 1), the a/d begins the conversion process on the current comparator input, unless a conversion cycle is currently under way. strtc is intended for use only at times when the a/d conversion process is not controlled by the antenna diversity logic. that is, whenever rxs=0, writing a 1 to strtc will; however, initiate a conversion cycle regardless of the state of the rxs bit of tir16. tir27: serial approximation register this register is the sar register. contains the a/d con- verter's serial approximation register value. a read from this register will give the current value of the sar in the a/d circuit. bit name reset value description 7 cact 0 conversion active. when an a/d conversion is being performed, the AM79C930 device will set this bit to a 1. when the conversion operation has completed, the AM79C930 device will reset this bit to a 0. 6C0 sar[6:0] pin serial approximation register. contains the a/d converter's serial approximation register value. a read from this register will give the current value of the sar in the a/d circuit. when cact is a 1, then this value is not stable. a write to this register will cause the written value to be driven onto the sar[6:0] pins if the adda bit of tir26 is set to 1. if the adda bit of tir26 is set to 0, then a write to sar[6:0] bits of tir27 will have no effect on the internal a/d conversion proc- ess or on the sar[6:0] output pins. p r e l i m i n a r y amd 103 AM79C930 tir28: rssi lower limit this register is the rssi lower limit register. the value in this register is compared against converted rssi in- put values. when the converted rssi value is equal to or exceeds the value in this register, then an indication will be sent to the clear channel assessment logic. bit name reset value description 7 rsalt 0 rssi equal or above limit. when the converted rssi input value equals or exceeds the value in the rssi lower limit register, then the AM79C930 device will set this bit to a 1. when the converted rssi input value is less than the value in the rssi lower limit regis- ter, then the AM79C930 device will set this bit to a 0. 6C0 rllt[6:0] 00h rssi lower limit. the value in this register is compared against converted rssi input values. when the converted rssi value equals or exceeds the value in this register, then an indication will be sent to the clear channel assessment logic. tir29: user pin data this register is the user pin data register. this register allows access to the user[4:0] pins. bit name reset value description 7 user7dl pin user7 pin data. the value that is written to this bit will be inverted and then driven out to the user7 pin of the AM79C930 device when the system interface mode is pcmcia and the user7en bit of tcr14 is set to one. in all other cases, the value of usr7dl will have no effect on the value of the user7 pin. the value that is read from this bit represents the inverted value of the user7 pin of the AM79C930 device at any time in any mode. the complete control of the function of the user7/irq11 pin is de- scribed in the multi-function pin section. 6 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. 5 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. 4C0 userdt[4:0] pin user pin data[4:0]. the value that is written to any bit of this regis- ter will be driven out to the corresponding user pin of the AM79C930 device when the corresponding useren bit of tcr14 has been set to a 1 and the pcmcia pin is set to 1. the value that is read from any bit of this register represents the current value of the corresponding user pin of the AM79C930 device regardless of useren bit or pcmcia pin settings. the complete control of the function of each of the user pins is de- scribed in the multi-function pin section. tir30: test dummy register this register is the test dummy register. bit name reset value description 7C0 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. amd p r e l i m i n a r y 104 AM79C930 tir31: test the tai test register is a reserved location. bit name reset value description 7 reserved 0 these bit must be set to 0. do not write to this register. 6C0 tc[6:0] 00h test command. the bits in this register are decoded to generate a test mode for the tai. tai configuration register space (tcr) the transceiver attachment interface (tai) unit con- tains a total of 64 registers. thirty-two of the registers are directly accessible from the 80188 embedded core and from the system interface through the biu. the other 32 registers are indirectly accessed by first writing an index value into the configuration register index (tir24) and then executing a read or write operation to the configuration data port (tir25). since the indirectly accessible registers are used mostly for tai configura- tion purposes, this set of registers is labeled tai con- figuration registers (tcr). the following section describes the indirectly accessible configuration regis- ters of the tai, or tcr. tcr0: network configuration this register is the network configuration register. configuration register index: 00h bit name reset value description 7C5 drb[2:0] 0h dribbling bits. the value of drb sets the amount of time that drib- bling bits will be generated following the end of crc during frame transmission. power will be removed from the transmitter following the end of the dribbling bit period. with respect to external transmit timing signals, the value of drb will determine the amount of time that passes from the sending of the last valid tx crc bit until the deassertion of the txp _ on signal. dribbling bit resolution is equal to 40 times the clkin period when the clkgt20 bit of mir9 is set to 0 and is equal to 80 times the clkin period when the clkgt20 bit of mir9 is set to 1. for a 1 mbs data rate with clkin = 20 mhz and clkgt20 = 0, the resolution is 2 m . 4C2 hdb[2:0] 0h header bits. the value of hdb sets the amount of time that header bits will be generated before the first bit of preamble is sent to the transmitter during frame transmission. the count begins at the time that power is applied to the transmitter. with respect to external transmit timing signals, the value of hdb will determine the amount of time that passes from the assertion of the txp _ on and signal to the delivery of the first valid tx data bit to the txdata pin. header bit resolution is equal to 40 times the clkin period when the clkgt20 bit of mir9 is set to 0 and is equal to 80 times the clkin period when the clkgt20 bit of mir9 is set to 1. for a 1 mbs data rate with clkin = 20mhz and clkgt20 = 0, the resolution is 2 m . 1C0 sd[1:0] 0h start delimiter. the value in this register determines the number of bytes of preamble that will be verified before the start of frame detect indication is asserted during frame reception and transmission. the following interpretations have been assigned to these bits. p r e l i m i n a r y amd 105 AM79C930 programmed sd[1:0] start of frame detect operation register 00 start of frame detect off none 01 search for 8 bit start of frame delimiter tcr10 10 search for 16 bit start of frame delimiter tcr9, tcr10 11 search for 24 bit start of frame delimiter tcr8, tcr9 tcr10 tcr1: transmit configuration this register is the transmit configuration register. configuration register index: 01h bit name reset value description 7 txendcb 0 transmit enable dc bias control. when txendcb is set to a 1, then the dc bias control algorithm is enabled. when txendcb is reset to a 0, then the dc bias control algorithm is disabled. 6C5 reserved 0 reserved. these bits may be written with any value. the value writ- ten to these bits will be returned when read. the value of these bits will not affect device function. 4 txdi 0 transmit data invert. when set to a 1, the outgoing transmit serial data stream is inverted. when set to a 0, the outgoing transmit se- rial data stream is not inverted. 3C2 txdlc 0 transmit data pin control. these bits are used to control the state of the txdl pin when no transmit activity is present. the following interpretations have been assigned to these bits: txdata pin txdlc[1:0] default state 00 last bit transmitted 01 high impedance 10 low 11 high 1C0 txdc 01b transmit data pin control. these bits are used to control the state of the txdl pin when no transmit activity is present. the following interpretations have been assigned to these bits: txdata pin txdc[1:0] default state 00 last bit transmitted 01 low 10 low 11 high amd p r e l i m i n a r y 106 AM79C930 tcr2: clock recovery this register is the clock recovery configuration register. bit name reset value description configuration register index: 02h 7 wns2 0 bit stuffing start. when wns2 is set to a 1, then the bit stuffing op- eration on rx and tx frames will begin after the phy header field has passed. when wns2 is set to a 0, then the bit stuffing function on rx and tx frames will begin operation immediately following start of frame delimiter detection. note that bit stuffing may be dis- abled with control bits in tcr1 (tx) and tcr3 (rx). 6 clkrs 0 clock recovery select. this bit selects between the two clock recovery circuits. 5 eclk 0 external receive clock select. when this bit is set to 1, then the device will expect a receive clock on the rxcin pin. when this bit is set to a 0, then the internal clock recovery circuit selected by the clkrs bit will be used to internally generate a recovered receive clock from the incoming receive data stream. 4:0 clkp[4:0] 0 clock phase. these bits are used to select the phase of the recov- ered rx clock relative to the rx data edges. valid values are 0 through 19 decimal, where each bit of resolution represents a shift in the phase of the sample point by one clkin period when the clkgt20 bit of mir9 is set to 0, and two clkin periods when the clkgt20 bit of mir9 is set to 1. tcr3: receive configuration this register is the receive configuration register. configuration register index: 03h bit name reset value description 7 loopb 0 loopback. when set to a 1, a loopback mode is enabled. when set to a 0, normal receive and transmit paths are followed. 6 wns 0 endian mode select. when set to a 1, this bit selects big endian (ms bit first) as the data format. the setting of this bit only affects the operation of the parallel-to-serial conversion register in the transmit path and the serial-to-parallel conversion register in the re- ceive path. no other areas are affected, i.e., start of frame detection is always performed on the bit stream as it will appear on the me- dium. when set to 0, little endian mode (ls bit first) is selected. 5 rxendcb 0 receive enable dc bias control. when rxendcb is set to a 1, then the receive machine will automatically remove the dc bias control effects from the input data stream. when rxendcb is reset to a 0, then the receive stream dc bias removal circuit will be disabled. 4 rxdi 0 receive data invert. when set to a 1, the incoming receive serial data stream is inverted. when set to a 0, the incoming receive serial data stream is not inverted. 3:0 pfl[3:0] 0 physical layer field length [3:0]. these bits are used to determine the number of bytes of phy header that are allowed to pass before the AM79C930 device begins calculating the crc8 and crc32 and dc bias control. the physical layer field length value is used p r e l i m i n a r y amd 107 AM79C930 to delay the start of crc8 and crc32 and dc bias control calculation for both receive and transmit frames. the physical header field is assumed to begin after the start of frame delimiter has been detected. tcr4: antenna diversity timer this register is the antenna diversity timer register used to control antenna dwell time during antenna diversity measurements. configuration register index: 04h bit name reset value description 7 anten 0 antenna diversity enable. when set to a 1, the internal antenna di- versity logic is used to select the antenna. when set to a 0, software has control over antenna selection through the ants bit of tir26[4] and the antsltld bit of tcr7[1]. dwell times for an- tenna measurements are still used to obtain rssi data when this bit is set to 0, but final antenna selection will be controlled by software. 6 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. 5C0 adt[5:0] 00h antenna diversity timer. dwell time per antenna in time steps of clkin period times 20 when the clkgt20 bit of mir9 is set to 0, and time steps of clkin period times 40, when the clkgt20 bit of mir9 is set to 1. when the value in this register is 00, then the di- versity switching function is disabled. tcr5: tx ramp up timing this register is the tx ramp up timing register. this register determines the ramp up timing of the tx enable signals. configuration register index: 05h bit name reset value description 7:4 tgap1[3:0] 0h transmit timing gap 1. these bits are used to determine the gap between the assertion of the t1 signal and the assertion of the t2 signal. t1 and t2 can be used to control the timing of the txcmd and txpe pins, respectively. the interval is programmable with a resolution equal to 20 times the clkin period when the clkgt20 bit of mir9 is set to 0 and a resolution equal to 40 times the clkin period when the clkgt20 bit of mir9 is set to 1. for a 1mbs data rate with clkin = 20mhz and clkgt20 = 0, the resolution is 1 m . 3:0 tgap2[3:0] 0h transmit timing gap 2. these bits are used to determine the gap between the assertion of the t2 signal and the assertion of the t3 signal. the interval is programmable with a resolution equal to 20 times the clkin period when the clkgt20 bit of mir9 is set to 0 and a resolution equal to 40 times the clkin period when the clkgt20 bit of mir9 is set to 1. for a 1 mbs data rate with clkin = 20 mhz and clkgt20 = 0, the resolution is 1 m . amd p r e l i m i n a r y 108 AM79C930 tcr6: tx ramp down timing this register is the tx ramp down timing register. this register determines the ramp down timing of the tx enable signals. configuration register index: 06h bit name reset value description 7:4 tgap3[3:0] 0h transmit timing gap 3. these bits are used to determine the gap between the deassertion of the t3 signal and the deassertion of the t2 signal. t3 and t2 can be used to control the timing of the txmod and txpe pins. the interval is programmable with a reso- lution equal to 20 times the clkin period when the clkgt20 bit of mir9 is set to 0 and a resolution equal to 40 times the clkin period when the clkgt20 bit of mir9 is set to 1. for a 1 mbs data rate with clkin = 20 mhz and clkgt20 = 0, the resolution is 1 m . 3:0 tgap4[3:0] 0h transmit timing gap 4. these bits are used to determine the gap between the deassertion of the t2 signal and the deassertion of the t1 signal. t2 and t1 can be used to control the timing of the txpe and txcmd pins. the interval is programmable with a resolution equal to 20 times the clkin period when the clkgt20 bit of mir9 is set to 0 and a resolution equal to 40 times the clkin period when the clkgt20 bit of mir9 is set to 1. for a 1mbs data rate with clkin = 20 mhz and clkgt20 = 0, the resolution is 1 m . tcr7: pin data a this register is the pin data a register. this register is used to deliver and retrieve data from the antslt , txdata and txcmd pins and to configure the function of the user5 and user6 pins. configuration register index: 07h bit name reset value description 7 ctsen 0 cts enable. when ctsen is set to a 1, then the user1/irq12 pin input value will be used to gate the start of the internal tx state ma- chine. with ctsen set to a 1, t1 , t2 , etc., signaling will not follow the assertion of the txs bit of tir8 until user1/irq12/extcts becomes active (high), and then normal timing for t1 , t2 , etc., will be produced. when ctsen is set to a 0, then tx state machine operations pro- ceed without delay, following the assertion the txs bit of tir8, re- gardless of the value of user1/irq12/extcts. 6 user6fn 0 user6 function. user6fn, the pcmcia mode pin, user6en (tcr15[3]), and the isa plug and play registers 70h and 71h are used to determine the function of the user6/irq5 pin. in addition, the user6/irq5 pin may be used to produce interrupts to the 80188 embedded controller. this capability is controlled by the enxsdf bit of tcr28 and the sdfu bit of tir5 and operates independently of the bits mentioned above. the control of the function of the user6/irq5 pin is described in the multi-function pin section. 5 user5fn 0 user5 function. user5fn, the pcmcia mode pin, user5en (tcr15[2]), and isa pnp registers 70h and 71h are used to deter- mine the function of the user5/irq4 pin. p r e l i m i n a r y amd 109 AM79C930 in addition, the user5/irq4 pin may be used to produce interrupts to the 80188 embedded controller. this capability is controlled by the enxchbsy bit of tcr28 and the chbsycu bit of tir5 and operates independently of the bits mentioned above. the control of the function of the user5/irq4 pin is described in the multi-function pin section. 4C3 u1intcnt 00b user1 interrupt control bits. the user1/irq12 pin can be used to signal an interrupt to the 80188 embedded controller. the u1intcnt bits have the following interpretation and operate inde- pendently of the operating mode of the AM79C930 device (i.e., the u1intcnt bits operate in both pcmcia and isa plug and play modes.): u1int bit u1intcnt user1 pin (tcr11[3]) tcr7[4:3] event result 00 x 0 => interrupt disabled 01 rising edge 1 => interrupt signaled 10 falling edge 1 => interrupt signaled 11 rising or 1 => interrupt falling edge signaled note that the user1 pin function has no effect on the use of the user1/irq12 pin as an interrupt signaling pin. if the user1/irq12 pin is to be used as a 80188 controller interrupt source in the isa plug and play mode, then it is imperative that the isa plug and play resource data structure loaded into the accom- panying flash device as part of the AM79C930 device based design should not include irq12 as a choice of irq level for possible se- lection by the isa plug and play configuration software. when this procedure is followed, then the system designer can be assured that the irq12 function will not be used by the AM79C930 device, and therefore, the user1/irq12 pin will remain in the high-imped- ance state and will be available for connection to an interrupt gener- ating source in the design. 2 txcmdt 0 txcmd data. the value written to the txcmdt bit is used in some modes to determine the output value of the txcmd/la21 pin. reads from txcmdt always return the current value of the txcmd/la21 pin. the control of the function of the txcmd/la21 pin is described in the multi-function pin section. 1 antsltld 1 antsltl data. the value that is written to this bit will be driven out to the antslt pin of the AM79C930 device when the antsltlfn bit of tcr30 has been set to a 1 and the antsltlen bit of tcr15 has also been set to a 1 and the pcmcia pin is set to 1. the value that is read from this bit represents the current value of the antslt pin of the AM79C930 device. a complete description of the control of the function of the antslt pin is described in the multi-function pin section. 0 txdatald 1 txdatal data. the value that is written to this bit will be driven out to the txdata pin of the AM79C930 device when the txdatalfn bit of tcr30 has been set to a 1 and the txdatalen bit of tcr15 amd p r e l i m i n a r y 110 AM79C930 has also been set to a 1 and the pcmcia pin is set to 1. the value that is read from this bit represents the current value of the txdata pin of the AM79C930 device. a complete description of the control of the function of the txdata pin is described in the multi-function pin section. tcr8: start delimiter lsb this register is the start delimiter lsb register. configuration register index: 08h bit name reset value description 7C0 sdlt[7:0] 00h start of frame delimiter. this register contains the lsb of the 24-bit start delimiter field that is used for start of frame recognition during reception and transmission in order to determine the start of mac crc calculation. (note that pfl of tcr3 may also affect start of mac crc calculation start.) all, none or part of the 24-bit start de- limiter may be used for start of frame recognition by appropriate set- tings of the sd[1:0] bits in the network configuration register (tcr0). start of frame detection is performed on the bits in the or- der that they appear on the medium, with the sdlt lsb, bit 0, being checked against the first bit to arrive at the AM79C930 (rx case) or the first bit to leave the AM79C930 (tx case) and continuing in that order. tcr9: start delimiter csb this register is the start delimiter csb register. configuration register index: 09h bit name reset value description 7C0 sdlt[15:8] 00h start of frame delimiter. this register contains the center signifi- cant byte (csb) of the 24-bit start delimiter field that is used for start of frame recognition during reception and transmission in order to determine the start of mac crc calculation. (note that pfl of tcr3 may also affect start of mac crc calculation start.) all, none or part of the 24-bit start delimiter may be used for start of frame recognition by appropriate settings of the sd[1:0] bits in the net- work configuration register (tcr0). start of frame detection is performed on the bits in the order that they appear on the medium, with the sdlt lsb, bit 0, being checked against the first bit to arrive at the AM79C930 (rx case) or the first bit to leave the AM79C930 (tx case) and continuing in that order. tcr10: start delimiter msb this register is the start delimiter msb register. configuration register index: 0ah bit name reset value description 7C0 sdlt[23:16] 00h start of frame delimiter. this register contains the msb of the 24-bit start delimiter field that is used for start of frame recognition during reception and transmission in order to determine the start of mac crc calculation. (note that pfl of tcr3 may also affect start of mac crc calculation start.) all, none or part of the 24-bit start p r e l i m i n a r y amd 111 AM79C930 delimiter may be used for start of frame recognition by appropriate settings of the sd[1:0] bits in the network configuration register (tcr0). start of frame detection is performed on the bits in the or- der that they appear on the medium, with the sdlt lsb, bit 0, being checked against the first bit to arrive at the AM79C930 (rx case) or the first bit to leave the AM79C930 (tx case) and continuing in that order. tcr11: interrupt register 3 this register is the tai interrupt register 3. provides in- terrupt status information. any interrupt bit may be cleared by writing a 1 to the bit location. writing a 0 to a bit location has no effect on the bit value. an interrupt in tcr11 will be signaled in tir4 through the moreint bit when the associated unmask bit has been set in tcr12. configuration register index: 0bh bit name reset value description 7:4 reserved C reserved. must be written as a 0. reads of these bits produce undefined data. 3 u1int 0 user1 interrupt. when u1int is set to 1, it indicates that a change of state has occurred at the user1/irq12 pin. the change of state required to signal an interrupt on the u1int bit is determined by the settings of the u1intsc bits of tcr7[4:3]. this function may be disabled with an appropriate setting of the u1intsc bits. a corre- sponding unmask bit for this interrupt source exists in tcr12. 2 runerr 1 run length error. when runerr is set to a 1, it indicates that the total number of 1s during a received message exceeds the total number of 0s at any given time by 25, or that the total number of 0s in the message at any given time exceeds the number of 1s in the message by 27. this function may be disabled with the disrnr bit of tcr27. 1 atfo 0 asynchronous transmit fifo overflow. when atfo is set to 1, it indicates that the asynchronous transmit fifo has overflowed. 0 atfu 0 asynchronous transmit fifo underflow. when atfu is set to 1, it indicates that the asynchronous transmit fifo has underflowed. tcr12: interrupt unmask register 3 this register is the interrupt unmask register 3. each bit in this register will unmask the corresponding interrupt of the interrupt register 2 (tir5) when the un- mask bit is set to 1. configuration register index: 0ch bit name reset value description 7:4 reserved C reserved. must be written as a 0. reads of these bits produce undefined data. 3 u1intu 0 user1 interrupt unmask. 2 runerru 0 runerr interrupt unmask. 1 atfou 0 asynchronous transmit fifo overflow interrupt unmask. 0 atfuu 0 asynchronous transmit fifo underflow interrupt unmask. amd p r e l i m i n a r y 112 AM79C930 tcr13: pin configuration a this register is the pin configuration a register. this register is used to set the state of various pins as outputs or as high impedance inputs. configuration register index: 0dh bit name reset value description 7 lnken 1 link led enable. lnken can be used to control the function of the lnk led output. the control of the function of the lnk pin is de- scribed in the multi-function pin section. 6 lfpeen 1 lfpe enable. lfpeen is used to determine the function of the lfpe pin. the control of the function of the lfpe pin is described in the multi-function pin section. 5 hfpeen 1 hfpe enable. hfpeen is used to determine the function of the hfpe pin. the control of the function of the hfpe pin is described in the multi-function pin section. 4 sdclken 1 sdclk enable. sdclken is used to determine the function of the sdclk pin. the control of the function of the sdclk pin is de- scribed in the multi-function pin section. 3 sds3len 1 sdsel3 enable. sds3len is used to determine the function of the sdsel3 pin. the control of the function of the sdsel [ 3 ] pin is de- scribed in the multi-function pin section. 2 sds2len 1 sdsel2 enable. sds2len is used to determine the function of the sdsel2 pin. the control of the function of the sdsel [ 2 ] pin is de- scribed in the multi-function pin section. 1 sds1len 1 sdsel1 enable. sds1len is used to determine the function of the sdsel1 pin. the control of the function of the sdsel [ 1 ] pin is de- scribed in the multi-function pin section. 0 rxpelen 1 rxpe enable. rxpelen is used to determine the function of the rxpe pin. the control of the function of the rxpe pin is described in the multi-function pin section. tcr14: pin configuration b this register is the pin configuration b register. this register is used to set the state of the user[4:0] pins as outputs or as high impedance inputs. configuration register index: 0eh bit name reset value description 7 user7en 0 user7 enable. user7en, the isa pnp registers 70h and 71h, and the pcmcia pin setting are used to determine the function of the user7 pin. the user7 pin can be programmed to function as either an input or an output. the control of the function of the user7/irq11 pin is described in the multi-function pin section. 6 llocken 0 llocke enable. llocken and the pcmcia pin are used to de- termine the direction of the llocke/sa15 pin. when llocken is set to a 1 and the pcmcia pin is set to 1, then the llocke/sa15 pin is enabled to drive both high and low output values. llocke output values are determined by the llocke bit of tir11. when llocken is reset to a 0, then the llocke pin is forced to a high- impedance state. reads of the llocke bit of tir11 will yield the p r e l i m i n a r y amd 113 AM79C930 value that is present on the llocke pin, regardless of the setting of the pcmcia pin. the control of the function of the llocke/sa15 pin is described in the multi-function pin section. 5 reserved C reserved. must be written as a 0. reads of these bits produce undefined data. 4:0 useren[4:0] 00h user[4:0] enable. these five bits are used to determine the direc- tion of the user[4:0] pins. when any bit of the useren register is set to a 1, then the corresponding user device pin is enabled to drive both high and low output values. user output values are de- termined by the individual bit settings of the userdt register (tir29). when any bit of the useren register is reset to a 0, then the corresponding user device pin is forced to a high-impedance state. reads of the userdt register (tir29) will yield the value that is present on any particular user pin. the control of the function of each of the user pins is described in the multi-function pin section. tcr15: pin configuration c this register is the pin configuration c register. this register is used to set the state of the act , stschg , user5, user6, rxc, txcmd, txdata , and antslt pins as outputs or as high impedance inputs. configuration register index: 0fh bit name reset value description 7 antsltlen 0 antslt enable. antsltlen, the antsltlfn bit of tcr30, the antsen bit of tir26, and the pcmcia pin are used to determine the function of the antslt /la23 pin. the control of the function of the antslt /la23 pin is described in the multi-function pin section. 6 txdlen 0 txdata enable. txdlen, the txdlfn bit of tcr30, and the pcmcia pin are used to determine the direction of the txdata / la20 pin. the control of the function of the txdata /la20 pin is described in the multi-function pin section. 5 txcmen 0 txcmd enable. txcmen, the txcmfn bit of tcr30, the rcen bit of tir11 and the pcmcia pin are used to determine the direc- tion of the txcmd/la21 pin. the control of the function of the txcmd/la21 pin is described in the multi-function pin section. 4 rxcen 0 rxc enable. rxcen is used with rxcfn (tcr28[7]), the isa pnp interrupt level select register, the isa pnp interrupt type regis- ter, and the pcmcia pin to determine the function of the rxc/ irq10 pin. the control of the function of the rxc/irq10 pin is described in the multi-function pin section. 3 user6en 0 user6 enable. user6en, the user6fn bit of tcr15, the isa pnp interrupt level select register, the isa pnp interrupt type regis- ter, and the pcmcia pin are used to determine the function of the user6irq5 pin. the control of the function of the user6/irq5 pin is described in the multi-function pin section. amd p r e l i m i n a r y 114 AM79C930 in addition to these bits, the user6/irq5 pin may be used to pro- duce interrupts to the 80188 embedded controller. this capability is controlled by the enxsdf bit of tcr28 and the sdfu bit of tir5 and operates independently of the bits in the table above. 2 user5en 0 user5 enable. user5en, the user5fn bit of tcr15, the isa pnp interrupt level select register, the isa pnp interrupt type regis- ter, and the pcmcia pin are used to determine the function of the user5irq4 pin. the control of the function of the user5/irq4 pin is described in the multi-function pin section. in addition to these bits, the user5/irq4 pin may be used to pro- duce interrupts to the 80188 embedded controller. this capability is controlled by the enxchbsy bit of tcr28 and the chbsycu bit of tir5 and operates independently of the bits in the table above. 1 acten 1 activity led enable. this bit can be used to control the act led output. the control of the function of the act pin is described in the multi-function pin section. 0 stschgfn 1 stschg function. this bit is used to determine the function of the stschg pin. when this bit is set to a 1, then the value of the stschg pin is equal to the nand result of the mir9 stschgd bit value and the pcmcia ccsr wakeup bit value. when this bit is set to a 0, then the value of the stschg pin is equal to the inver- sion of the mir9 stschgd bit value. this function is only available in pcmcia mode. the complete control of the function of the stschg/bale pin is described in the multi-function pin section. tcr16: baud detect start this register is the baud detect start register. this reg- ister is used to program the start time for the baud de- tection circuit. the start time is compared against the current value of the antenna diversity timer and the baud detect test begins when the compare is true. note that the antenna diversity timer is a count down timer with an initial value specified in tcr4. if the automatic antenna diversity logic is disabled, then the antenna diversity timer continues to run and provide a reference point for the start of the baud detect start value. configuration register index: 10h bit name reset value description 7C6 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. 5C0 bds[5:0] 00h baud detect start. the value in this register is used to determine when the baud detection circuit will begin examining incoming rxd data. the baud detection begins when the antenna diversity timer of tcr4 reaches the value specified here as bds[5:0]. the an- tenna diversity timer is a count down timer operating at a resolution equal to 20 times the clkin period when the clkgt20 bit of mir9 is set to 0 and a resolution equal to 40 times the clkin period when the clkgt20 bit of mir9 is set to 1. for a 1 mbs data rate with clkin = 20 mhz and clkgt20 = 0, the resolution is 1 m . p r e l i m i n a r y amd 115 AM79C930 tcr17: baud detect lower limit this register is the baud detect lower limit register (tcr17). configuration register index: 11h bit name reset value description 7C6 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. 5C0 bdllt[5:0] 00h baud detect lower limit. this register is used to program the lower limit for the baud detection circuit. the lower limit defines the short- est time between like transitions (i.e., rising edge to rising edge or falling edge to falling edge) that is expected for a given baud rate. if like transitions are separated by values below this limit, then the baud detect test for that pair of like transitions will fail. note that the rising edge baud counter will begin counting from 0 and when it reaches a value of 29, the next increment will cause the counter to wrap to a value of 10 decimal. the falling edge baud counter operates in an identical manner. therefore, rising edges that are separated by 20, 40, 60, 80, etc. clkin periods (with clkgt20=0 each baud tick is one clkin period, with clkgt20=1, each baud tick is two clkin periods) will all yield a rising edge baud counter value of 20. the same is true for the falling edge baud counter. this information should be used to appropri- ately program the baud detect lower limit register. the resolution of the value in this register is the period of the clkin signal when the clkgt20 bit of mir9 is set to 0 or twice the period of the clkin signal when the clkgt20 bit of mir9 is set to 1. with clkin = 20 mhz and clkgt20=0, a value of 14h (=20 decimal) represents the nominal pulse width value for 1 mbit/s network data rate operation. tcr18: baud detect upper limit. this register is the baud detect upper limit register. configuration register index: 12h bit name reset value description 7C6 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. 5C0 bdult[5:0] 00h baud detect upper limit. this register is used to program the upper limit for the baud detection circuit. the upper limit defines the long- est time between like transitions (i.e., rising edge to rising edge or falling edge to falling edge) that is expected for a given baud rate. if like transitions are separated by values above this limit, then the baud detect test for that pair of like transitions will fail. note that the rising edge baud counter will begin counting from 0 and when it reaches a value of 29, the next increment will cause the counter to wrap to a value of 10 decimal. the falling edge baud counter operates in an identical manner. therefore rising edges that are separated by 20, 40, 60, 80, etc. clkin periods (with clkgt20=0 each baud tick is one clkin period, with clkgt20=1, each baud tick is two clkin periods) will all yield a rising edge baud counter value of 20. the same is true for the falling amd p r e l i m i n a r y 116 AM79C930 edge baud counter. this information should be used to appropri- ately program the baud detect upper limit register. the resolution of the value in this register is the period of the clkin signal when the clkgt20 bit of mir9 is set to 0 or twice the period of the clkin signal when the clkgt20 bit of mir9 is set to 1. with clkin = 20 mhz and clkgt20=0, a value of 14h (=20 decimal) represents the nominal like transition separation value for a 1mbit/s network data rate. tcr19: baud detect accept count for carrier sense this register is the baud detect accept count for carrier sense register. when the number of positive baud de- tect test results in the baud detection circuit reaches the value in this register, then the total number of tests taken to that point will be considered adequate to make a valid determination of positive carrier sense. the number of positive baud detect test results is reset to 0 each time that the antenna selection is changed. configuration register index: 13h bit name reset value description 7C6 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. 5C0 bdcs[5:0] 00h baud detect accept count for carrier sense. when the number of positive baud detect test results in the baud detection circuit reaches the value in this register, then the total number of tests taken to that point will be considered adequate to make a valid de- termination of positive carrier sense. the number of positive baud detect test results is reset to 0 each time that the antenna selection is changed. tcr20: baud detect accept count for stop diversity this register is the baud detect accept count for stop diversity register. when the number of positive baud de- tect test results in the baud detection circuit reaches the value in this register, then the total number of tests taken to that point will be considered adequate to make a valid determination of satisfactory antenna selection. the number of positive baud detect test results is reset to 0 each time that the antenna selection is changed. configuration register index: 14h bit name reset value description 7C6 reserved C reserved. must be written as a 0. reads of this bit produce unde- fined data. 5C0 bdsd[5:0] 00h baud detect accept count for stop diversity. when the number of positive baud detect test results in the baud detection circuit reaches the value in this register, then the total number of tests taken to that point will be considered adequate to make a valid de- termination of satisfactory antenna selection. the number of posi- tive baud detect test results is reset to 0 each time that the antenna selection is changed. tcr21: baud detect ratio this register is the baud detect ratio register. this reg- ister is used to set the ratio of good to bad baud detec- tions which will be used as the minimum ratio to determine that a valid signal is present on the medium. the value in this register is treated as a radix 2 positive real number with two decimal places. the lowest practi- cal value possible is 0.25 (=00.01) and the highest prac- tical value is 3.75 (=11.11). p r e l i m i n a r y amd 117 AM79C930 configuration register index: 15h bit name reset value description 3C0 bdrn[3:0] 0h baud detect ratio. these bits are used to set the ratio of good to bad baud detections which will be used as the minimum ratio to de- termine that a valid signal is present on the medium. the value in this register is treated as a radix 2 positive real number with two decimal places. the lowest practical value possible is 0.25 (=00.01) and the highest practical value is 3.75 (=11.11). tcr22: baud detect accept count this register is the baud detect accept count register. a read-only register that indicates the current number of good transitions detected by the baud detector. configuration register index: 16h bit name reset value description 7C6 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. 5C0 acpt[5:0] 00h accept[5:0] the value of these bits indicates the current number of good transitions detected by the baud detector. this is a read-only register. tcr23: baud detect fail count this register is the baud detect fail count register. a read-only register that indicates the current number of bad transitions detected by the baud detector. configuration register index: 17h bit name reset value description 7C6 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. 5C0 fail[5:0] 00h fail[5:0] the value of these bits indicates the current number of bad transitions detected by the baud detector. this is a read-only register. tcr24: rssi sample start this register is the rssi sample start register. the value in this register is used to determine when to cap- ture a sample of the rssi input for a/d conversion dur- ing antenna diversity operation. the register value is a measure of the time of rssi sample relative to the an- tenna switching event. a register value of 0 means that no rssi samples will be taken. amd p r e l i m i n a r y 118 AM79C930 configuration register index: 18h bit name reset value description 7:6 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. 5:0 ss[5:0] 00h rssi sample start. the value in this register is used to determine when to capture a sample of the rssi input for a/d conversion dur- ing antenna diversity operation. the register value is a measure of the time of rssi sample relative to the end of the current antenna dwell time (i.e., ss=03h implies that the rssi sample will be con- verted at 3 m s before the current antenna dwell time ends). the resolution of the rssi sample timer is equal to 20 times the clkin period when the clkgt20 bit of mir9 is set to 0 and is equal to 40 times the clkin period when the clkgt20 bit of mir9 is set to 1. for a 1 mbs data rate with clkin = 20 mhz and clkgt20 = 0, the resolution is 1 m . with clkin=20 mhz and clkgt20 = 0, a value of ss[5:0] = 00100 means that the rssi sample will be taken 4 m before the next antenna switch event occurs. a register value of 0 means that no rssi samples will be taken. the time value represented by the bits in ss[5:0] must be less than the time value of the bits in the adt[5:0] field of tcr4 minus the time value of the bits of the a2dt[3:0] field of tcr25 minus 9 clkin periods (18 clkin periods if clkgt20=1). tcr25: rssi configuration this register is the rssi configuration register. this register is used to setup some a/d converter parameters. configuration register index: 19h bit name reset value description 7 uxa2dst 0 use external a/d conversion start signal. when uxa2dst is set to 0, then the a/d conversion process starts when the antenna dwell timer reaches the value programmed in the ss bits of tcr24. when uxa2dst is set to 1, then an external stimulus from the user6/irq5/exta2dst pin is required to begin each a/d conver- sion cycle. rising edges of user6/irq5/exta2dst initiate new conversion cycles. a/d sample and conversion timing will proceed as programmed in the tcr25 register a2dt field. 6 enext 0 enable external. setting enext to a 1 enables the external a/d mode of the AM79C930 device, allowing the AM79C930 device to use the digital values supplied by an external a/d converter in cca and antenna diversity decisions. enext is used in conjunction with ensar (tcr25[5]) and adda (tir26[2]) to configure the AM79C930 device a/d mode according to the table listed in section rssi a/d unit . 5 ensar 0 enable sar. setting ensar to a 1 enables the sar[6:0] pins to drive as outputs. ensar is used in conjunction with enint (tcr25[6]) and adda (tir26[2]) to configure the AM79C930 de- vice a/d mode according to the table listed in the rssi a/d unit de- scription of in section rssi a/d unit . 4 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. p r e l i m i n a r y amd 119 AM79C930 3C0 a2dt[3:0] 1010b a/d sampling time[3:0]. the value in the a2dt[3:0] field deter- mines the duration of time required to convert the a/d input. each bit of resolution is equal to 4 times the clkin period when the clkgt20 bit of mir9 is set to 0 and is equal to 8 times the clkin period when the clkgt20 bit of mir9 is set to 1. for a 1mbs data rate with clkin = 20 mhz and clkgt20 = 0, the resolution is 200 n. the a2dt value is used by all a/d modes, including the mode that uses the internal a/d converter. the internal a/d converter requires 600 nsec to convert C note that the default value of this reg- ister is 2.0 m s for a clkin equal to 20mhz with the clkgt20 bit set to 0. note that the actual time for conversion is less than the a2dt pro- grammed value by 1.5 clkin periods (with clkgt20=0, it is 3 clkin periods if clkgt20=1). this fact is important when using an external a/d converter in the external a/d mode. minimum value in the a2dt[3:0] field must be 0001. a value of 0000 is not allowed. note: adin1, adin2, and sar_latch signals are only valid as shown when enext (tcr25[6]) has been set to a 1. 20138b-9 antslt ta = period of clkin when clkgt20 = 0 ta = (period of clkin) x 2 when clkgt20 = 1 cca_test (internal signal) start_a2d (internal signal) adt[5:0]=tcr4[5:0] cact=tir27[7] ss[5:0]=tcr24[5:0] 2 x ta a2dt[3:0]=tcr25[3:0]+4 x ta adin1 (when enext=1) adin2 (when enext=1) sar_latch (internal signal) 6 x ta ta 6 x ta 1 x ta 3 x ta 3 x ta 3 x ta sar[6:0] when ensar = 1 figure 3. analog-to-digital state machine timing amd p r e l i m i n a r y 120 AM79C930 tcr26: reserved this register is the tai reserved location register. configuration register index: 1ah bit name reset value description 7C0 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. tcr27: tip led scramble this register is the network interface polarity register. this register is used to set the polarity of some of the transceiver interface output pins. configuration register index: 1bh bit name reset value description 7 disrnr 0 disable runerr. when disrnr is set to a 1, then the runerr bit of tcr11 will always be held at a 0 value. when disrnr is set to a 0, then the runerr bit of tcr11 will function as described in the tcr11 bit description. 6 reserved C reserved. must be written as a 0. reads of these bits produce undefined data. 5 reserved 0 reserved. must be written as a 0. reads of these bits produce undefined data. 4 lnkdr 0 lnk pin drive. when set to a 0, the drive of the lnk pin will be open drain. when set to a 1, the drive of the lnk pin will be totem pole, i.e., both high and low output values will be driven. complete control of the function of the lnk pin is described in the multi-function pin section. 3 actdr 0 act pin drive. when set to a 0, the drive of the act pin will be open drain. when set to a 1, the drive of the act pin will be totem pole, i.e., both high and low output values will be driven. complete control of the function of the act pin is described in the multi-function pin section. 2 fdetpol 0 fdet polarity. when this bit is set to a 0, then the polarity of the fdet output will be low assert, such that when the sfd pattern has been recognized in the incoming receive data stream or the outgo- ing transmit data stream, the fdet pin will be driven to a low logic level. when this bit is set to a 1, then the polarity of the fdet output will be high assert, such that when the sfd pattern has been recog- nized in the incoming receive data stream or the outgoing transmit data stream, the fdet pin will be driven to a high logic level. 1 txpepol 0 txpe polarity. when this bit is set to a 0, then the polarity of the txpe output will be low assert, such that when the tgap1 counter expires, the txpe pin will be driven to a low logic level. when this bit is set to a 1, then the polarity of the txpe output will be high as- sert, such that when the tgap1 counter expires, the txpe pin will be driven to a high logic level. 0 txmodpol 0 txmod polarity. when this bit is set to a 0, then the polarity of the txmod output will be low assert, such that when the tgap2 counter expires, the txmod pin will be driven to a low logic level. when this bit is set to a 1, then the polarity of the txmod output will p r e l i m i n a r y amd 121 AM79C930 be high assert, such that when the tgap2 counter expires, the txmod pin will be driven to a high logic level. tcr28: clear channel assessment configuration this register is the clear channel assessment configuration register. the bits in this register are used to determine which features will be used to determine clear channel assessment. configuration register index: 1ch bit name reset value description 7 rxcfn 0 rxc function. when rxcfn is set to a 1, then the rxc pin will be driven with the internal rxc clock value, regardless of its source. that is, the rxc source may be either the result of the dpll locking operation, or it may directly reflect the value of the rxcin pin, de- pending upon the selection of the eclk bit of tcr2. complete control of the function of the rxc/irq10 pin is described in the multi-function pin section. 6 enxsdf 0 enable external start delimiter found. when enxsdf is set to a 1, then the internal sdf result is not used. instead, the value of the user6/irq5 pin is used as the source for sdf indication. when enxsdf is set to 1, then changes to the value of the user6/irq5 pin are used to determine the status of the sdf interrupt of tir5 (bit 2). when enxsdf is set to 0, then the source for sdf indication is the internal sdf determination logic. the current drive and function settings for the user6/irq5 pin have no effect on the use of the value of this pin for the sdf function. 5 enxchbsy 0 enable external chbsy. when enxchbsy is set to a 1, then the internal cca result is not used. instead, the value of the user5/irq4 pin is used as the source for cca information. when enxchbsy is set to 1, the value of the user5/irq4 pin is used to set the value of the chbsy bit of tir26 (bit 7), and changes to the value of the user5/irq4 pin are used to determine the status of the chbsyc interrupt of tir4 (bit 7) and the bcf interrupt bit of tir5. when enxchbsy is set to a 1, then antenna diversity switching is disabled and the receive function of the AM79C930 device must be enabled by a positive indication of sdf on the user6/irq5 input pin. when enxchbsy is set to 0, then the source for cca indication is the internal cca determination logic. the current drive and function settings for the user6/irq5 pin have no effect on the use of the value of this pin for the sdf function. 4 rupd 0 receive use preamble detect. when rupd is set to a 1, then the stop diversity decision is used to enable the receive state machine. that is, when the decision is made to stop switching antenna selec- tions, then the receive state machine will enable the receive data path to the rx fifo. when rupd is reset to a 0, then the receive data path to the rx fifo is enabled when sfd is detected. 3 stpen 0 stop antenna diversity enable. setting this bit to a 1 allows the clear channel assessment logic to stop the antenna diversity operation. 2 ubdsd 0 use baud detect of stop diversity in antenna diversity decision. when this bit is set to a 1, the baud detect count for stop diversity becomes one input to the stop diversity decision logic. when this bit amd p r e l i m i n a r y 122 AM79C930 is set to a 0, the baud detect count for stop diversity is not used in the stop diversity decision logic. 1 ubdcs 0 use baud detect of carrier sense in cca decision. when this bit is set to a 1, the baud detect count for carrier sense becomes one input to the clear channel assessment logic. when this bit is set to a 0, the baud detect count for carrier sense is not used in the clear channel assessment decision. 0 urssi 0 use rssi in cca and stop diversity decisions. when this bit is set to a 1, the rssi converted value comparison to the rssi lower limit becomes one input to the clear channel assessment logic and also becomes one input to the stop diversity decision logic. when this bit is set to a 0, the rssi converted value comparison to the rssi lower limit is not used in the clear channel assessment logic and is also not used in the stop diversity decision logic. tcr29: reserved this register is a tai reserved location. configuration register index: 1dh bit name reset value description 7C0 reserved C reserved. must be written as a 0. reads of this bit produce undefined data. tcr30: pin function and data rate this register is the pin function and data rate control register. this register contains bits that control the function of the antslt , txdata , txcmd, and txc pins as well as control bits to set the network data rate. configuration register index: 1eh bit name reset value description 7 antsltlfn 0 antslt function. antsltlfn, antsltlen (tcr15[7]), antsen (tir26[3]), and the pcmcia pin are used to determine the direction and data of the antslt pin. the control of the function of the antslt /la23 pin is described in the multi-function pin section. 6 txdlfn 0 txdata function. txdlfn, txdlen (tcr15[6]), and the pcmcia pin are used to determine the direction and data of the txdata pin. the control of the function of the txdata /la23 pin is described in the multi-function pin section. 5 txcmfn 0 txcmd function. txcmfn, txcmen (tcr15[5]), rcen (tir11[3]), and the pcmcia pin are used to determine the function of the txcmd pin. 4 user7fn C reserved. must be written as 0. reads of this produce undefined data. the control of the function of the txcmd/la21 pin is described in the multi-function pin section. 3 txcin 1 txc input. when set to a 0, the txc pin functions as an output, pro- viding a divide by x version of the clkin input, where x is deter- mined by the setting of the dr bits of tcr30. when set to a 1, the txc pin functions as an input, allowing the data rate of the transmit operations to be set by an external source. when txcin is set to 1, p r e l i m i n a r y amd 123 AM79C930 then a 16-bit deep serial fifo is inserted into the tx data path. this fifo allows for some mismatch to be tolerated in the clock rates between the AM79C930 internal transmit clock and the external txc clock that is connected to the txc input. because of this inter- nal fifo, the appearance of transmit data from the setting of the txs bit in tir8 will be delayed by 8 bit times whenever the txcin bit has the value of 1. the control of the function of the txc pin is described in the multi- function pin section. 2:0 dr[2:0] 001b data rate. the value in this register determines the data rate for the network. the txc output pin will be affected. the following inter- pretations have been assigned to these bits: dr[2:0] clkgt20 network tcr30[2:0] mir9[7] data rate 000 0 reserved 001 0 f clkin 20 010 0 f clkin 40 011 0 f clkin 80 100 0 reserved 101 0 f clkin 200 110 0 f clkin 2000 111 0 reserved 000 1 f clkin 20 001 1 f clkin 40 010 1 f clkin 80 011 1 f clkin 160 100 1 reserved 101 1 f clkin 400 110 1 f clkin 4000 111 1 reserved the data rate bits are used together with the clkgt20 bit to con- trol clock divider circuits in the dpll section of the tai and in the transmit state machine section of the tai. specifically, the dpll clock source will always be set at a rate of 20 times the desired net- work data rate in order to provide the appropriate amount of over- sampling to insure proper dpll tracking of the incoming signal. the transmit state machine section of the tai logic will receive a divided clock that is equal to the desired network data rate. note that if the clkin frequency is greater than 20 mhz, then the clkgt20 bit must be set to 1. tcr31: device revision this register is the device revision register. configuration register index: 1fh bit name reset value description 7C0 rev[7:0] 01h revision number. the value in this field contains the revision num- ber for the current device. the lowest revision number is 01h. amd p r e l i m i n a r y 124 AM79C930 pcmcia ccr registers and pcmcia cis space two bytes of attribute memory space have been used by the AM79C930 device for storage of two card configuration registers. these two registers are found at attribute memory locations 800h and 802h. the configuration option register is located at attribute memory location 800h and the card configuration and status register is located at attribute memory location 802h. because the location of these registers is fixed at 800h and 802 in attribute memory space, then the value of the ccr offset located in the tpcc_radr field of the con- figuration tuple must be equal to 800h. pcmcia configuration option register this register is used to configure the AM79C930 device and to issue a soft reset to the AM79C930 device. the pcmcia configuration option register is located at the fixed attribute memory location 0802h. therefore, the information programmed into the cis must give the value 2k (=0800h) as the card configuration registers base address in the tpcc_radr field of the configu- ration tuple. the configuration option register is lo- cated at tpcc_radr + 2. the following tables indicate the bits that are supported in the configuration option registers: bit name reset value description 7 sreset 0 resets AM79C930 device. setting this bit to 1 places the AM79C930 device into the reset state, which is equivalent to the as- sertion of the pcmcia reset signal. this bit does not reset itself back to 0. 6 levelreq 0 level mode interrupts when levelreq = 1. pulse mode interrupts when levelreq = 0. 5:0 conf index 0 configuration index. this field is written with the index number of the entry in the card's configuration table which the system chooses for this card. when conf index = 00000, then the AM79C930 device is in memory only mode. when any of these five bits is set to 1, then the i/o interface is enabled, meaning that i/o transfers are allowed. pcmcia card configuration and status register this register contains information about the card's condition. the pcmcia card configuration and status register is located at the fixed attribute memory location 0802h. therefore, the information programmed into the cis must give the value 2k (=0800h) as the card configura- tion registers base address in the tpcc_radr field of the configuration tuple. the card configuration and status register is located at tpcc_radr + 2. bit name reset value description 7:6 reserved C read only as a 0. 5 iois8 0 this bit is written by the host to indicate that the host is only capable of 8-bit i/o accesses. this bit is ignored by the AM79C930 device, since the AM79C930 device is only capable of 8-bit i/o accesses. 4 wakeup 0 wakeup is used with the stschgfn bit of tcr15 to determine the function of the stschg pin. when the stschgfn bit of tcr15 is set to 1, then the wakeup bit is nanded with the value of the stschgd bit of mir8 and the result is driven onto the stschg pin. when the stschgfn bit of tcr15 is set to 0, then the stschg pin becomes an output that is controlled by the stschgd bit of mir8. 3 read-back 0 read/write bit C serves no other function. 2 power down 0 requests the 80188 to enter power down mode. if already in power down mode, this bit will indicate 1. when written with a 1, value read will remain 0 until the device actually enters the power down mode. p r e l i m i n a r y amd 125 AM79C930 when written with a 1, the pwrdwn bit generates an interrupt to the 80188, requesting that the 80188 core place the AM79C930 de- vice into the power down state. the interrupt is signaled in mir0, bit 5. if written with a 0 while in power down mode, power down mode is exited. when written with a 1, value read will remain 0 until the de- vice actually enters the power down mode. 1 interrupt C represents the internal interrupt level. this signal remains true un- til the interrupt has been serviced (not pulse generated). 0 reserved C read only as a 0. pcmcia card information structure (cis) the pcmcia cis space has been allocated to reside in the flash memory space of a design based on the AM79C930 device. this space corresponds to 1kC16 bytes of the uppermost 1k of flash memory. since only even addressed bytes of attribute memory space are defined to exist in the pcmcia specification, only even addresses of the 2kC32 cis range will map into the flash memory, and hence, the 2kC32 address range for the AM79C930 cis space is mapped to only 1kC16 bytes of flash space. note that the address range is limited to 2kC32 rather than a complete 2k of space. this is because the upper- most 16 bytes of the flash memory must be reserved for the initial instructions for the 80188 core, since the 80188 core will automatically access these locations for its initial instruction fetch following a AM79C930 device reset operation. amd p r e l i m i n a r y 126 AM79C930 absolute maximum ratings storage temperature: C65 to +150 c . . . . . . . . . . . . ambient temperature under bias: C65 to +125 c . . . supply voltage to av ss or dv ss (av dd , dv dd ): C0.3 to +6 v . . . . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices temperature (t a )0 c to + 70 c . . . . . . . . . . . . . . . . . supply voltages (av dd , v cc , v ddt , v ddu1 , v ddu2 , v ddm , v ddp , v dd5 ) +5 v 5% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . all inputs within the range: av ss C 0.5 v v in . . . . . av dd + 0.5 v, or dv ss C 0.5 v v in dv dd + 0.5 v operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics 5.0 v AM79C930 dc characteristics parameter symbol parameter description test conditions min max units v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol1 = 4 ma 0.45 v i ol2 = 12 ma 0.45 i ol3 = 24 ma 0.45 (note 1, 5) v oh output high voltage (note 2) i oh = C.4 ma (note 5) 2.8 v v olc output low voltage for i ol = 0.2 ma 0.1 x v dd v cmos only load v ohc output high voltage for i oh = C0.2 ma 0.9 x v dd v cmos only load i ix input leakage current (note 3) v dd = 5 v, v in = 0 v C10 10 m a v ilx xtal1 input low voltage threshold v in = external clock C0.5 0.8 v v ihx xtal1 input high voltage threshold v in = external clock 3.5 v dd + 0.5 v i ilx xtal1 input low current v in = external clock (active) C100 m a v in = v ss (power down) C10 +10 m a i ihx xtal1 input high current v in = external clock (active) 100 m a v in = v dd (power down) 400 m a i ozl output leakage current (note 4) v out = 0.4 v C10 m a i ozh output leakage current (note 4) v out = v dd 10 m a i ddf power supply current clkin = 40 mhz, 150 ma pmx1 = 32.768 khz i dds power supply current clkin = 20 mhz, 85 ma pmx1 = 32.768 khz i ddpd1 power supply current power down mode 45 ma clkin = internally cutoff, pmx1 = 32.768 khz, no host interface accesses occurring v in v il or v in 3 v ih p r e l i m i n a r y amd 127 AM79C930 dc characteristics (continued) 5.0 v AM79C930 dc characteristics parameter symbol parameter description test conditions min max units i ddpd2 power supply current power down mode 40 ma clkin = internally cutoff, pmx1 = 32.768 khz, no host interface accesses occurring v in v ol or v in 3 v oh i ddpd3 power supply current power down mode 900 m a clkin = internally cutoff, pmx1 = 32.768 khz, no host interface accesses occurring v in v olc or v in 3 v ohc c in input pin capacitance f c = 1 mhz (note 6) 12 pf c o i/o or output pin capacitance f c = 1 mhz (note 6) 12 pf c clk bclk pin capacitance f c = 1 mhz (note 6) 12 pf notes: 1. i ol1 = 4ma applies to the following pins: stschg , pwrdwn, ma[16:0], md[7:0], fce, sce, xce, moe, mwe, tdo, lfpe , lfclk, llocke, hfpe, inpack, hfclk, antslt, antslt, txcmd, txcmd, txpe, txdata, txdata, txmod, rxpe, fdet, sdclk, sddata, sdsel [3:1], sar[6:0], user[4:2], user[0], txc, adin1, adin2. i ol2 = 12 ma applies to the following pins: act, lnk i ol3 = 24 ma applies to the following pins: d[7:0], wait, ireq , user5, user6, rxc, user7, user[1] 2. v oh does not apply to open-drain output pins. 3. does not apply to pmx1, pmx2, and adref. 4. i ozh and i ozl apply to all three-state output pins and bidirectional pins. 5. outputs are cmos and will be driven to rail if the load is not resistive to supply. 6. not 100% tested. value determined by characterization. amd p r e l i m i n a r y 128 AM79C930 absolute maximum ratings storage temperature: C65 to +150 c . . . . . . . . . . . . ambient temperature under bias: C65 to +125 c . . . supply voltage to av ss or dv ss (av dd , dv dd ): C0.3 to +6 v . . . . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices temperature (t a )0 c to + 70 c . . . . . . . . . . . . . . . . . supply voltages (av dd , v cc , v ddt , v ddu1 , v ddu2 , v ddm , v ddp , v dd5 ) 3.0 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . supply voltages (av dd , v dd5 ) +5 v 5% . . . . . . . . . . . . . . . . . . . . . . . . all inputs within the range: av ss C 0.5 v v in . . . . . av dd + 0.5 v, or dv ss C 0.5 v v in dv dd + 0.5 v operating ranges define those limits between which the func- tionality of the device is guaranteed. 3.3 v AM79C930 dc characteristics parameter symbol parameter description test conditions min max units v il input low voltage C0.3 0.8 v v ih input high voltage 2.0 v dd + 0.3 v v ol output low voltage i ol1 = 2.4 ma 0.4 v i ol2 = 12 ma 0.4 i ol3 = 8 ma 0.4 (note 1, 5) v oh output high voltage (note 2) i oh = C0.4 ma (note 5) 2.4 v v olc output low voltage for i ol = 0.2 ma v cmos only load v ohc output high voltage for i ol = C0.2 ma v dd C 0.2 v cmos only load i ix input leakage current (note 3) v dd = 5 v, v in = 0 v C10 10 m a v ilx xtal1 input low voltage threshold v in = external clock C0.5 0.8 v v ihx xtal1 input high voltage threshold v in = external clock 3.5 v dd + 0.5 v i ilx xtal1 input low current v in = external clock (active) C100 m a v in = dv ss (power down) C10 +10 m a iihx xtal1 input high current v in = external clock (active) 100 m a v in = v dd (power down) 400 m a i ozl output leakage current (note 4) v out = 0.4 v C10 m a i ozh output leakage current (note 4) v out = v dd 10 m a i ddf power supply current clkin = 40 mhz, 105 ma pmx1 = 32.768 khz i dds power supply current clkin = 20 mhz, 60 ma pmx1 = 32.768 khz i ddpd1 power supply current power down mode 15 ma clkin = internally cutoff, pmx1 = 32.768 khz, no host interface accesses occurring v in v il or v in v ih p r e l i m i n a r y amd 129 AM79C930 dc characteristics (continued) 3.3 v AM79C930 dc characteristics parameter symbol parameter description test conditions min max units i ddpd2 power supply current power down mode 5 ma clkin = internally cutoff, pmx1 = 32.768 khz, no host interface accesses occurring v in v il or v in v oh i ddpd3 power supply current power down mode 900 m a clkin = internally cutoff, pmx1 = 32.768 khz, no host interface accesses occurring v in v olc or v in 3 v ohc c in input pin capacitance f c = 1 mhz (note 6) 12 pf c o i/o or output pin capacitance f c = 1 mhz (note 6) 12 pf c clk bclk pin capacitance f c = 1 mhz (note 6) 12 pf notes: 1. i ol1 = 2.4ma applies to the following pins: stschg , pwrdwn, ma[16:0], md[7:0], fce, sce, xce, moe, mwe, tdo, lfpe , lfclk, llocke, hfpe, inpack, hfclk, antslt, antslt, txcmd, txcmd, txpe, txdata, txdata, txmod, rxpe, fdet, sdclk, sddata, sdsel [3:1], sar[6:0], user[4:2], user[0], txc, adin1, adin2. i ol2 = 12 ma applies to the following pins: act, lnk i ol3 = 8 ma applies to the following pins: d[7:0], wait, ireq , user5, user6, rxc, user7, user[1] 2. v oh does not apply to open-drain output pins. 3. does not apply to pmx1, pmx2, and adref. 4. i ozh and i ozl apply to all three-state output pins and bidirectional pins. 5. outputs are cmos and will be driven to rail if the load is not resistive to supply. 6. not 100% tested. value determined by characterization. amd p r e l i m i n a r y 130 AM79C930 absolute maximum ratings storage temperature: C65 to +150 c . . . . . . . . . . . . ambient temperature under bias: C65 to +125 c . . . supply voltage to av ss or dv ss (av dd , dv dd ): C0.3 to +6 v . . . . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices temperature (t a )0 c to + 70 c . . . . . . . . . . . . . . . . . supply voltages (v cc , v ddt , v ddu1 , v ddu2 , v ddm , v ddp ) +5 v 5% or 3.0 v to 3.6 v . . . . . . . . . . . . . . . . . . . . supply voltages (av dd , v dd5 ) +5 v 5% . . . . . . . . . . . . . . . . . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. ieee 1149.1 dc characteristics (5.0 and 3.3 v) parameter symbol parameter description test conditions min max units v il tck, tms, tdi, trst 0.8 v v ih tck, tms, tdi, trst 2.0 v v ol tdo i ol = 2.0 ma 0.4 v v oh tdo i oh = C0.4 ma 2.4 v i il tck, trst v dd = 5.5 v, v i = 0.5 v C400 m a i ih tck, trst v dd = 5.5 v, v i = 2.7 v C200 m a i il tms, tdi v dd = 5.5 v, v i = 0.5 v C400 m a i ih tms, tdi v dd = 5.5 v, v i = 2.7 v C200 m a i ozl tdo v out = 0.4 v C10 m a i ozh tdo v out = v dd +10 m a p r e l i m i n a r y amd 131 AM79C930 ac characteristics 5.0 and 3.3 v pcmcia interface absolute maximum ratings storage temperature: C65 to +150*c . . . . . . . . . . . . ambient temperature under bias: C65 to +125*c . . . supply voltage to av ss or dv ss (av dd , dv dd ): C0.3 to +6 v . . . . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices temperature (t a )0 c to + 70 c . . . . . . . . . . . . . . . . . supply voltages (v cc , v ddt , v ddu1 , v ddu2 , v ddm , v ddp ) 3.0 v to 5.25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltages (av dd , v dd5 ) +5 v 5% . . . . . . . . . . . . . . . . . . . . . . . . all inputs within the range: v ss C 0.5 v v in v dd + 0.1 x v dd C where v ss and v dd are appropriate reference pins for a given input pin. (see section on power supply pin descriptions.) cl = 50 pf unless otherwise noted operating ranges define those limits between which the func- tionality of the device is guaranteed. pcmcia memory read access parameter symbol parameter description test conditions min max unit t avqv address access time note 1 0 550 ns t avgl address setup to oe 5ns t ghax address hold from oe - 20 ns t elqv ce access time note 1 0 550 ns t elgl ce setup to oe 0ns t gheh ce hold from oe - (read) or ce hold from we - (write) 20 ns t glqv oe acess time note 1 0 200 ns t glwtv wait valid from oe 35 ns t wtlwth wait pulse width notes 2, 3 53 x t clkin ns t glqnz data bus driven from oe note 3 0 ns t qvwth data setup to wait - 0ns t ghqz data disabled from oe - note 3 90 ns notes: 1. assumes no wait state access is programmed. 2. the max value for this parameter assumes the following worst case situation: value worst case 0 flash and sram wait states set at 3. 1 host performs pcmcia write cycle at same time that AM79C930 embedded 80188 controller begins instruction fetch cycle to flash memory. 2 pcmcia write cycle is posted internal to AM79C930 device, pending the completion of the embedded 80188 controller access. 3 host performs pcmcia read cycle immediately following completion of pcmcia write cycle. 4 after completion of first embedded 80188 access to flash, posted pcmcia write executes to sram; pcmcia read stycle is being held in wait state. 5 after completion of posted isa write cycle, new embedded 80188 access to flash begins. 6 after completion of second embedded 80188 access to flash, pcmcia read cycle is allowed to proceed onto memory bus to sram; host is still held in wait state. 7 at sram read cycle completion, data is delivered to pcmcia bus and wait state is exited. 3. parameter is not included in production test. amd p r e l i m i n a r y 132 AM79C930 pcmcia memory write access parameter symbol parameter description test conditions min max unit t avwl address setup to we 20 ns t avwh address setup to we - 100 ns t wmax write recovery time (address hold from we - )20ns t elwh ce setup to we - 140 ns t elwl ce setup to we 0ns t gheh ce hold from oe - (read) or ce hold from we - (write) 20 ns t ghwl oe setup to we 10 ns t whgl oe hold from we - 10 ns t wlwh we pulse width 120 ns t wlwtv wait valid from we 35 ns t wtlwth wait pulse width notes 1, 2 53 x t clkin ns t wthwh we hold from wait - 0ns t dvwh data setup to we - 60 ns t wmdx data hold from we - 30 ns t ghqz data disabled from oe - note 2 90 ns t wlqz data disabled from we note 2 90 ns t whqnz data enabled from we - note 2 5 ns t glqnz data enabled from oe note 2 5 ns notes: 1. the max value for this parameter assumes the following worst case situation: value worst case 0 flash and sram wait states set at 3. 1 host performs pcmcia write cycle at same time that AM79C930 embedded 80188 controller begins instruction fetch cycle to flash memory. 2 pcmcia write cycle is posted internal to AM79C930 device, pending the completion of the embedded 80188 controller access. 3 host performs pcmcia read cycle immediately following completion of pcmcia write cycle. 4 after completion of first embedded 80188 access to flash, posted pcmcia write executes to sram; pcmcia read stycle is being held in wait state. 5 after completion of posted isa write cycle, new embedded 80188 access to flash begins. 6 after completion of second embedded 80188 access to flash, pcmcia read cycle is allowed to proceed onto memory bus to sram; host is still held in wait state. 7 at sram read cycle completion, data is delivered to pcmcia bus and wait state is exited. 2. parameter is not included in production test. p r e l i m i n a r y amd 133 AM79C930 pcmcia i/o read access parameter symbol parameter description test conditions min max unit t avigl address setup to iord 70 ns t ighax address hold from iord - 20 ns t rgligl reg setup to iord 5ns t ighrgh reg hold from iord - 0ns t eligl ce setup to iord 5ns t igheh ce hold from iord - 20 ns t igligh iord width 165 ns t iglial inpack delay from iord 045ns t ighiah inpack - delay from iord - 45 ns t iglwtl wait delay from iord 35 ns t wtlwth wait width notes 1, 2 53 x t clkin ns t wthqv data delay from wait - 0ns t iglqnz data enabled from iord note 2 0 ns t iglqv data delay from iord 100 ns t ighqx data hold from iord - 0ns t ighqz data disabled from iord - note 2 20 ns notes: 1. the max value for this parameter assumes the following worst case situation: value worst case 0 flash and sram wait states set at 3. 1 host performs pcmcia write cycle at same time that AM79C930 embedded 80188 controller begins instruction fetch cycle to flash memory. 2 pcmcia write cycle is posted internal to AM79C930 device, pending the completion of the embedded 80188 controller access. 3 host performs pcmcia read cycle immediately following completion of pcmcia write cycle. 4 after completion of first embedded 80188 access to flash, posted pcmcia write executes to sram; pcmcia read stycle is being held in wait state. 5 after completion of posted isa write cycle, new embedded 80188 access to flash begins. 6 after completion of second embedded 80188 access to flash, pcmcia read cycle is allowed to proceed onto memory bus to sram; host is still held in wait state. 7 at sram read cycle completion, data is delivered to pcmcia bus and wait state is exited. 2. parameter is not included in production test. amd p r e l i m i n a r y 134 AM79C930 pcmcia i/o write access parameter symbol parameter description test conditions min max unit t aviwl address setup to iowr 70 ns t iwhax address hold from iowr - 20 ns t rgliwl reg setup to iowr 5ns t iwhrgh reg hold from iowr - 0ns t eliwl ce setup to iowr 5ns t iwheh ce hold from iowr - 20 ns t iwliwh iowr width 165 ns t iwlwtl wait delay from iowr 35 ns t wtlwth wait width notes 1, 2 53 x t clkin ns t wthiwh iowr - from wait - 0ns t dviwl data setup to iowr 60 ns t iwhdx data hold from iowr - 30 ns notes: 1. the max value for this parameter assumes the following worst case situation: value worst case 0 flash and sram wait states set at 3. 1 host performs pcmcia write cycle at same time that AM79C930 embedded 80188 controller begins instruction fetch cycle to flash memory. 2 pcmcia write cycle is posted internal to AM79C930 device, pending the completion of the embedded 80188 controller access. 3 host performs pcmcia read cycle immediately following completion of pcmcia write cycle. 4 after completion of first embedded 80188 access to flash, posted pcmcia write executes to sram; pcmciisa read stycle is being held in wait state. 5 after completion of posted pcmcia write cycle, new embedded 80188 access to flash begins. 6 after completion of second embedded 80188 access to flash, pcmcia read cycle is allowed to proceed onto memory bus to sram; host is still held in wait state. 7 at sram read cycle completion, data is delivered to pcmcia bus and wait state is exited. 2. parameter is not included in production test. p r e l i m i n a r y amd 135 AM79C930 ac characteristics 5.0 and 3.3 v isa interface absolute maximum ratings storage temperature: C65 to +150 c . . . . . . . . . . . . ambient temperature under bias: C65 to +125 c . . . supply voltage to av ss or dv ss (av dd , dv dd ): C0.3 to +6 v . . . . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices temperature (t a )0 c to + 70 c . . . . . . . . . . . . . . . . . supply voltages (v cc ,v ddt , v ddu1 , v ddu2 , v ddm , v ddp ) 3.0 v to 5.25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltages (av dd , v dd5 ) +5 v 5% . . . . . . . . . . . . . . . . . . . . . . . . all inputs within the range: v ss C 0.5 v v in v dd + 0.1 x v dd C where v ss and v dd are appropriate reference pins for a given input pin. (see section on power supply pin descriptions.) cl = 50 pf unless otherwise noted operating ranges define those limits between which the func- tionality of the device is guaranteed. amd p r e l i m i n a r y 136 AM79C930 isa access parameter symbol parameter description test conditions min max unit t i 1 la[23:17] valid setup to bale 60 ns t i 2 bale - to bale pulse width 25 ns t i 3 la[23:17] valid hold from bale 12 ns t i 4 la[23:17] valid setup to cmd note 1 80 ns t i 7 sa[16:0] valid setup to cmd note 1 25 ns t i 8 cmd to cmd - pulse width note 4 6*t clkin ns t i 9 sa[16:0] valid setup to bale 20 ns t i 10 data valid delay from rcmd notes 2, 5, 6 53 x t clkin ns t i 11 data valid setup to wcmd note 3 C75 ns t i 12 sa[16:0] valid hold from cmd - note 1 20 ns t i 13 cmd - to cmd pulse width note 1 55 ns t i 14 data valid hold from rcmd - note 2 0 ns t i 15 data valid hold from wcmd - note 3 20 ns t i 16 data disabled from rcmd - note 2, 6 20 ns t i 20 iochrdy delay from cmd notes 1, 7 60 ns t i 21 iochrdy to iochrdy - notes 5, 6, 7 0 130 + ns pulse width 53 x t clkin t i 22 cmd - delay from iochrdy - notes 1, 7 35 ns t i 23 bale - delay from cmd - note 1 20 ns t i 25 data valid delay from iochrdy - note 7 Ct clkin 25 ns t i 26 la[23:17] valid hold from cmd note 1 C15 ns t i 30 aen valid setup to cmd note 1 80 ns t i 31 aen valid hold from cmd - note 1 15 ns t i 32 aen valid setup to bale 60 ns t i 34 data enabled from rcmd notes 2, 4 0 110 ns notes: 1. cmd = one of: memr , memw , ior or iow . 2. rcmd = one of: memr , or ior . 3. wcmd = one of: memw , or iow . 4. if no wait states are incurred. 5. the max value for this parameter assumes the following worst case situation: value worst case 0 flash and sram wait states set at 3. 1 host performs isa write cycle at same time that AM79C930 embedded 80188 controller begins instruction fetch cycle to flash memory. 2 isa write cycle is posted internal to AM79C930 device, pending the completion of the embedded 80188 controller access. 3 host performs isa read cycle immediately following completion of isa write cycle. 4 after completion of first embedded 80188 access to flash, posted isa write executes to sram; isa read stycle is being held in wait state. 5 after completion of posted isa write cycle, new embedded 80188 access to flash begins. 6 after completion of second embedded 80188 access to flash, isa read cycle is allowed to proceed onto memory bus to sram; host is still held in wait state. 7 at sram read cycle completion, data is delivered to isa bus and wait state is exited. 6. parameter is not included in production test. 7. parameter only applies when iochrdy is deasserted. p r e l i m i n a r y amd 137 AM79C930 ac characteristics 5.0 v memory bus interface absolute maximum ratings storage temperature: C65 to +150 c . . . . . . . . . . . . ambient temperature under bias: C65 to +125 c . . . supply voltage to av ss or dv ss (av dd , dv dd ): C0.3 to +6 v . . . . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices temperature (t a )0 c to + 70 c . . . . . . . . . . . . . . . . . supply voltages (v cc , v ddt , v ddu1 , v ddu2 , v ddm , v ddp ) 4.75 v to 5.25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltages (av dd , v dd5 ) +5 v 5% . . . . . . . . . . . . . . . . . . . . . . . . all inputs within the range: v ss C 0.5 v v in v dd + 0.1 x v dd C where v ss and v dd are appropriate reference pins for a given input pin. (see section on power supply pin descriptions.) cl = 50 pf unless otherwise noted operating ranges define those limits between which the func- tionality of the device is guaranteed. memory bus read access parameter symbol parameter description test conditions min max unit t m ad ma[16:0] valid from clkin 260ns t m cd ce active delay from clkin note 1 2 60 ns t m od moe active delay from clkin 260ns t m olz moe to md[7:0] driven 0 wait states 0 30 ns (note 3) 1 wait state 80 ns 2 wait states 130 ns t m aa address read access time 0 wait states 55 ns (note 3) 1 wait state 105 ns 2 wait states 155 ns t m acs ce read access time 0 wait states 55 ns (notes 1, 3) 1 wait state 105 ns 2 wait states 155 ns t m oe moe read access time 0 wait states 30 ns (note 3) 1 wait state 80 ns 2 wait states 130 ns t m ri ce inactive time notes 1, 2 0 ns t m ah ma[16:0] valid hold from moe - note 1 t clkin -10 ns t m ch ce valid hold from moe - t clkin -10 ns t m h md[7:0] valid hold from moe - note 2 0 ns t m hz md[7:0] inactive from moe - note 2 0 2 x t clkin -15 ns notes: 1. ce = one of: fce , sce , xce 2. parameter not included in the production test. 3. value is dependent upon tclkin value. value given is for clkin = 40 mhz. amd p r e l i m i n a r y 138 AM79C930 memory bus write access parameter symbol parameter description test conditions min max unit t m ad ma[16:0] valid from clkin 260ns t m cd ce active delay from clkin note 1 2 60 ns t m wd mwe active delay from clkin 260ns t m cq md[16:0] driven from clkin 2ns t m cv md[16:0] valid from clkin 60 ns t m as address setup time to mwe t clkin -20 ns t m aw address write access time 0 wait states 95 ns (note 3) 1 wait state 145 ns 2 wait states 195 ns t m cw ce write access time 0 wait states 95 ns (notes 1, 3) 1 wait state 145 ns 2 wait states 195 ns t m wp mwe write access time 0 wait states 90 ns (note 3) 1 wait state 140 ns 2 wait states 190 ns t m wq mwe to md[7:0] driven C10 ns t m ah ma[16:0] valid hold from mwe - t clkin -10 ns t m ch ce valid hold from mwe - note 1 t clkin -10 ns t m wi ce inactive time note 1, 2 0 ns t m sw md[7:0] valid setup to mwe - 0 wait states 80 ns 1 wait state 130 ns 2 wait states 180 ns t m hw md[7:0] valid hold from mwe - note 2 t clkin -15 ns t m hwz md[7:0] inactive from mwe - note 2 2 x t clkin -10 2 x t clkin +10 ns notes: 1. ce = one of: fce , sce , xce 2. parameter not included in the production test. 3. value is dependent upon tclkin value. value given is for clkin = 40 mhz. p r e l i m i n a r y amd 139 AM79C930 ac characteristics 3.3 v memory bus interface absolute maximum ratings storage temperature: C65 to +150 c . . . . . . . . . . . . ambient temperature under bias: C65 to +125 c . . . supply voltage to av ss or dv ss (av dd , dv dd ): C0.3 to +6 v . . . . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices temperature (t a )0 c to + 70 c . . . . . . . . . . . . . . . . . supply voltages (v cc ,v ddt , v ddu1 , v ddu2 , v ddm , v ddp ) 3.0 v to 5.25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltages (av dd , v dd5 ) +5 v 5% . . . . . . . . . . . . . . . . . . . . . . . . all inputs within the range: v ss C 0.5 v v in v dd + 0.1 x v dd C where v ss and v dd are appropriate reference pins for a given input pin. (see section on power supply pin descriptions.) cl = 50 pf unless otherwise noted operating ranges define those limits between which the func- tionality of the device is guaranteed. memory bus read access parameter symbol parameter description test conditions min max unit t m ad ma[16:0] valid from clkin 2 100 ns t m cd ce active delay from clkin note 1 2 100 ns t m od moe active delay from clkin 2 100 ns t m olz moe to md[7:0] driven 0 wait states 0 70 ns (note 3) 1 wait state 170 ns 2 wait states 270 ns t m aa address read access time 0 wait states 120 ns (note 3) 1 wait state 220 ns 2 wait states 320 ns t m acs ce read access time 0 wait states 120 ns (notes 1, 3) 1 wait state 220 ns 2 wait states 320 ns t m oe moe read access time 0 wait states 70 ns (note 3) 1 wait state 170 ns 2 wait states 270 ns t m ri ce inactive time notes 1, 2 0 ns t m ah ma[16:0] valid hold from moe - note 1 t clkin -10 ns t m ch ce valid hold from moe - t clkin -10 ns t m h md[7:0] valid hold from moe - note 2 0 ns t m hz md[7:0] inactive from moe - note 2 0 2 x t clkin -15 ns notes: 1. ce = one of: fce , sce , xce 2. parameter not included in the production test. 3. value is dependent upon tclkin value. value given is for clkin = 20 mhz. amd p r e l i m i n a r y 140 AM79C930 memory bus write access parameter symbol parameter description test conditions min max unit t m ad ma[16:0] valid from clkin 2 100 ns t m cd ce active delay from clkin note 1 2 100 ns t m wd mwe active delay from clkin 2 100 ns t m cq md[7:0] driven from clkin 2ns t m cv md[7:0] valid from clkin 100 ns t m as address setup time to mwe t clkin -20 ns t m aw address write access time 0 wait states 160 ns (note 3) 1 wait state 260 ns 2 wait states 360 ns t m cw ce write access time 0 wait states 160 ns (notes 1, 3) 1 wait state 260 ns 2 wait states 360 ns t m wp mwe write access time 0 wait states 150 ns (note 3) 1 wait state 250 ns 2 wait states 350 ns t m wq mwe to md[7:0] driven C10 ns t m ah ma[16:0] valid hold from mwe - t clkin -10 ns t m ch ce valid hold from mwe - note 1 t clkin -10 ns t m wi ce inactive time note 1, 2 0 ns t m sw md[7:0] valid setup to mwe - 0 wait states 130 ns 1 wait state 230 ns 2 wait states 330 ns t m hw md[7:0] valid hold from mwe - note 2 t clkin -15 ns t m hwz md[7:0] inactive from mwe - note 2 2 x t clkin -10 2 x t clkin +10 ns notes: 1. ce = one of: fce , sce , xce 2. parameter not included in the production test. 3. value is dependent upon tclkin value. value given is for clkin = 20 mhz. p r e l i m i n a r y amd 141 AM79C930 ac characteristics 5.0 v tai interface absolute maximum ratings storage temperature: C65 to +150 c . . . . . . . . . . . . ambient temperature under bias: C65 to +125 c . . . supply voltage to av ss or dv ss (av dd , dv dd ): C0.3 to +6 v . . . . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices temperature (t a )0 c to + 70 c . . . . . . . . . . . . . . . . . supply voltages (v cc ,v ddt , v ddu1 , v ddu2 , v ddm , v ddp ) 3.0 v to 5.25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltages (av dd , v dd5 ) +5 v 5% . . . . . . . . . . . . . . . . . . . . . . . . all inputs within the range: v ss C 0.5 v v in v dd + 0.1 x v dd C where v ss and v dd are appropriate reference pins for a given input pin. (see section on power supply pin descriptions.) cl = 50 pf unless otherwise noted operating ranges define those limits between which the func- tionality of the device is guaranteed. amd p r e l i m i n a r y 142 AM79C930 5.0 v tai interface ac characteristics parameter symbol parameter description test conditions min max unit t clkin clkin period mir9[7]=1 25 ns t clin clkin low time mir9[7]=1 5 ns t chin clkin high time mir9[7]=1 5 ns t clkin clkin period mir9[7]=0 50 t clin clkin low time mir9[7]=0 22 t chin clkin high time mir9[7]=0 22 t inhl clkin fall time note 8 3 ns t inlh clkin rise time note 8 3 ns t rxc rxc period note 5 500 ns t clrx rxc low time note 5 240 ns t chrx rxc high time note 5 240 ns t rxhl rxc fall time note 8 10 ns t rxlh rxc rise time note 8 10 ns t txc txc period notes 1, 5, 7 500 ns t cltx txc low time notes 1, 5, 7 245 ns t chtx txc high time notes 1, 5, 7 245 ns t txhl txc fall time notes 1, 8 5 ns t txlh txc rise time notes 1, 8 5 ns t txco txc period notes 2, 7 500 ns t cltxo txc low time notes 2, 7 285 ns t chtxo txc high time notes 2, 7 185 ns t txhlo txc fall time notes 2, 8 15 ns t txlho txc rise time notes 2, 8 15 ns t rxds rxd setup time to rxc - note 6 110 ns t rxdh rxd hold time from rxc - note 6 10 ns t txdd txd delay from txc notes 1, 3 10 200 ns t txds txd setup time to txc - notes 2, 4 t cltx -165 ns t txdh txd hold time from txc - notes 2, 4 t chtx ns t txdv txd delay from txc notes 2, 3 0 150 ns p r e l i m i n a r y amd 143 AM79C930 notes: 1. only applicable when txc has been configured as an input. 2. only applicable when txc has been configured as an output. 3. min value not tested. 4. parameter calculated from other parameters. 5. clock period must correlate to data rate as specified in dr bits of tcr30. note that data rate is a function of dr and t clkin and clkgt20 bit of mir9. 6. the values for these parameters are given for the case with clkp = 0 (tcr2[4:0]). for nonzero values of clkp, use the following formulas: if clkgt20 = 0 (mir9[7]), t rxds min = 110Cclkp x t clkin t rxdh min = 10+clkp x t clkin if clkgt20 = 1 (mir9[7]), t rxds min = 110Cclkp x t clkin x 2 t rxdh min = 10+clkp x t clkin x 2 7. values given are for data rate of 2mb/s. for other data rates, t txc is 1/dr, where dr = data rate in hertz, t cltx is 60% of t txc minus t txhl , t chtx is 40% of t txc minus t txhl , t txco is 1/dr, where dr = data rate in hertz, t cltxo is 60% of t txco minus t txhlo , t chtxo is 40% of t txco minus t txhlo , t txhlo is 15 ns, regardless of dr value, t txlho is 15 ns, regardless of dr value. 8. parameter not included in the production test. amd p r e l i m i n a r y 144 AM79C930 ac characteristics 3.3 v tai interface absolute maximum ratings storage temperature: C65 to +150 c . . . . . . . . . . . . ambient temperature under bias: C65 to +125 c . . . supply voltage to av ss or dv ss (av dd , dv dd ): C0.3 to +6 v . . . . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices temperature (t a )0 c to + 70 c . . . . . . . . . . . . . . . . . supply voltages (v cc ,v ddt , v ddu1 , v ddu2 , v ddm , v ddp ) 3.0 v to 5.25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltages (av dd , v dd5 ) +5 v 5% . . . . . . . . . . . . . . . . . . . . . . . . all inputs within the range: v ss C 0.5 v v in v dd + 0.1 x v dd C where v ss and v dd are appropriate reference pins for a given input pin. (see section on power supply pin descriptions.) cl = 50 pf unless otherwise noted operating ranges define those limits between which the func- tionality of the device is guaranteed. p r e l i m i n a r y amd 145 AM79C930 3.3 v tai interface ac characteristics parameter symbol parameter description test conditions min max unit t clkin clkin period 50 ns t clin clkin low time 22 ns t chin clkin high time 22 ns t inhl clkin fall time note 8 3 ns t inlh clkin rise time note 8 3 ns t rxc rxc period note 5 1000 ns t clrx rxc low time note 5 480 ns t chrx rxc high time note 5 480 ns t rxhl rxc fall time note 8 20 ns t rxlh rxc rise time note 8 20 ns t txc txc period notes 1, 5, 7 1000 ns t cltx txc low time notes 1, 5, 7 495 ns t chtx txc high time notes 1, 5, 7 495 ns t txhl txc fall time notes 1, 8 5 ns t txlh txc rise time notes 1, 8 5 ns t txco txc period notes 2, 7 1000 ns t cltxo txc low time notes 2, 7 585 ns t chtxo txc high time notes 2, 7 385 ns t txhlo txc fall time notes 2, 8 15 ns t txlho txc rise time notes 2, 8 15 ns t rxds rxd setup time to rxc - note 6 110 ns t rxdh rxd hold time from rxc - note 6 10 ns t txdd txd delay from txc notes 1, 3 10 200 ns t txds txd setup time to txc - notes 2, 4 t cltx -165 ns t txdh txd hold time from txc - notes 2, 4 t chtx ns t txdv txd delay from txc notes 2, 3 0 150 ns notes: 1. only applicable when txc has been configured as an input. 2. only applicable when txc has been configured as an output. 3. min value not tested. 4. parameter calculated from other parameters. 5. clock period must correlate to data rate as specified in dr bits of tcr30. note that data rate is a function of dr and t clkin and clkgt20 bit of mir9. 6. the values for these parameters are given for the case with clkp = 0 (tcr2[4:0]). for nonzero values of clkp, use the following formulas: if clkgt20 = 0 (mir9[7]), t rxds min = 110Cclkp x t clkin t rxdh min = 10+clkp x t clkin if clkgt20 = 1 (mir9[7]), t rxds min = 110Cclkp x t clkin x 2 t rxdh min = 10+clkp x t clkin x 2 7. values given are for data rate of 1mb/s. for other data rates, t txc is 1/dr, where dr = data rate in hertz, t cltx is 60% of t txc minus t txhl , t chtx is 40% of t txc minus t txhl , t txco is 1/dr, where dr = data rate in hertz, t cltxo is 60% of t txco minus t txhlo , t chtxo is 40% of t txco minus t txhlo , t txhlo is 15 ns, regardless of dr value, t txlho is 15 ns, regardless of dr value. 8. parameter not included in the production test. amd p r e l i m i n a r y 146 AM79C930 ac characteristics 5.0 and 3.3 v user programmable pins absolute maximum ratings storage temperature: C65 to +150 c . . . . . . . . . . . . ambient temperature under bias: C65 to +125 c . . . supply voltage to av ss or dv ss (av dd , dv dd ): C0.3 to +6 v . . . . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices temperature (t a )0 c to + 70 c . . . . . . . . . . . . . . . . . supply voltages (v cc ,v ddt , v ddu1 , v ddu2 , v ddm , v ddp ) 3.0 v to 5.25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltages (av dd , v dd5 ) +5 v 5% . . . . . . . . . . . . . . . . . . . . . . . . all inputs within the range: v ss C 0.5 v v in v dd + 0.1 x v dd C where v ss and v dd are appropriate reference pins for a given input pin. (see section on power supply pin descriptions.) cl = 50 pf unless otherwise noted operating ranges define those limits between which the func- tionality of the device is guaranteed. parameter symbol parameter description test conditions min max units t u 1 data change delay from 55 ns clkin t u 2 pin drive disable delay from 55 ns clkin note 1 t u 3 pin drive enable delay from 55 ns clkin note 1 note: 1. parameter is not included in production test. p r e l i m i n a r y amd 147 AM79C930 ac characteristics 5.0 and 3.3 v ieee 1149.1 interface absolute maximum ratings storage temperature: C65 to +150 c . . . . . . . . . . . . ambient temperature under bias: C65 to +125 c . . . supply voltage to av ss or dv ss (av dd , dv dd ): C0.3 to +6 v . . . . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices temperature (t a )0 c to + 70 c . . . . . . . . . . . . . . . . . supply voltages (v cc ,v ddt , v ddu1 , v ddu2 , v ddm , v ddp ) 3.0 v to 5.25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltages (av dd , v dd5 ) +5 v 5% . . . . . . . . . . . . . . . . . . . . . . . . all inputs within the range: v ss C 0.5 v v in v dd + 0.1 x v dd C where v ss and v dd are appropriate reference pins for a given input pin. (see section on power supply pin descriptions.) cl = 50 pf unless otherwise noted operating ranges define those limits between which the func- tionality of the device is guaranteed. parameter symbol parameter description test conditions min max units t 25 tck period 100 ns t 30 tdi, tms setup time to tck - 16 ns t 31 tdi, tms hold time from tck - 10 ns t 32 tdo valid delay from tck 360ns t 34 all outputs (non-test) valid delay 3 60 ns from tck t 35 all outputs (non-test) float delay 70 ns from tck note 1 t 36 all inputs (non-test) setup time to 8 ns tck - t 37 all inputs (non-test) hold time from 25 ns tck - note: 1. parameter is not included in production test. analog-to-digital (a/d) converter characteristics resolution: 7 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . resolution tested: 4 bits . . . . . . . . . . . . . . . . . . . . . . sample rate: 1.66 msps (600 ns)* . . . . . . . . . . . . . . recommended a/d ref range: 1.25 to 1.75 v** . . . . range of adin1 + adin2: 0 to (adref x 2) . . . . . . . *user should program a 0011 in a2dt[3:0] of tcr25. **adref is doubled internally. amd p r e l i m i n a r y 148 AM79C930 timing waveforms pcmcia bus interface waveforms a n , reg ce oe d o (dout) t avqv t elqv t glqv t glqnz t ghax t ghqz we (high) wait t elgl t avgl t gheh t glwtv t wtlwth t qvwth 20138b-10 figure 4. pcmcia memory read access timing diagram a n , reg ce we d i (din) t elwh t wlwh t wmdx wait t elwl t avwl t whgl t wlwtv t wtlwth t dvwh d o (dout) oe t ghwl t wlqz t ghqz t gheh t glqnz t whqnz t avwh t wmax t wthwh 20138b-11 figure 5. pcmcia memory write access timing diagram p r e l i m i n a r y amd 149 AM79C930 20138b-12 a n reg iord d o (dout) wait t avigl ce t ighrgh t rgligl t ighax t eligl t igligh t iglwtl t wtlwth t igheh t wthqv t ighqx t iglqv inpack t iglial t ighiah t ighqz t igqnz figure 6. pcmcia i/o read access timing diagram a n reg iowr d i (din) wait t aviwl ce t iwhrgh t rgliwl ti whax t eliwl t iwliwh ti wlwtl t wtlwth ti wheh twthiwh t iwhdx t dviwl 20138b-13 figure 7. pcmcia i/o write access timing diagram amd p r e l i m i n a r y 150 AM79C930 isa bus interface waveforms 20138b-14 ** cmd = one of: memr , memw , ior , iow la n cmd** sd out (read) t i 1 t i 8 t i 34 t i 3 t i 14 iochrdy t i 7 t i 4 t i 20 aen bale sa n t i 2 t i 10 sd in (write) t i 11 t i 12 t i 13 t i 15 t i 21 t i 22 t i 23 t i 25 t i 26 t i 30 t i 31 t i 32 t i 9 t i 16 figure 8. isa all access timing diagram p r e l i m i n a r y amd 151 AM79C930 memory bus interface waveforms 20138b-15 ma n fce, sce, xce moe md i (din) t m aa t m oe t m ad mwe (high) clkin t m rdsc t m acs t m h data sampled at this point valid t m ri t m rdhc t m ad t m cd t m od t m olz t m hz clkout (internal) t m cd t m od t m ah t m ch figure 9. memory bus read access timing diagram 20138b-16 ma n fce, sce, xce moe md o (dout) t m aw t m wp t m ad mwe (high) clkin t m sw t m cw t m hw valid t m wi t m hwc t m ad t m cd t m wd t m wq t m hwz clkout (internal) t m cd t m wd t m hwzc t m ah t m ch t m cq t m cv t m as figure 10. memory bus write access timing diagram amd p r e l i m i n a r y 152 AM79C930 clock waveforms 20138b-17 clkin 0.8 v 2.0 v t clin t inhl t clkin t inlh t chin 0.8 v txc 0.8 v 2.0 v t cltx t txhl t txc t txlh t chtx 0.8 v rxc 0.8 v 2.0 v t clrx t rxhl t rxc t rxlh t chrx 0.8 v figure 11. clock timing diagram p r e l i m i n a r y amd 153 AM79C930 tai waveforms 20138b-18 **ico = internally controlled output ico* rco** rco** t n 1 clkin clkout (internal) t n 2 rco** t n 3 t n 4 figure 12. tai timing diagram 20138b-19 rxd t rxds rxc t rxds txd t txdd txc (input) txd t txdv txc (output) t txds t txdh figure 13. serial data timing diagram amd p r e l i m i n a r y 154 AM79C930 programmable interface waveforms 20138b-20 **rco = register controlled output wait or iochrdy rco** (data change) clkout (internal) rco** (drive change) t u 1 t u 2 rco** (drive change) t u 3 clkin figure 14. programmable interface timing diagram p r e l i m i n a r y amd 155 AM79C930 ieee 1149.1 interface waveforms 20138b-21 tck tdi, tms tdo t 31 output signals t 25 t 30 t 32 t 34 t 37 t 36 input signals t 35 figure 15. ieee 1149.1 timing diagram amd p r e l i m i n a r y 156 AM79C930 ac test reference waveforms 5.0 v pcmcia ac test reference waveform this waveform indicates the ac testing method em- ployed for all signals that are pcmcia bus signals when the pcmcia power supply pins are set to 5.0 v (i.e., vddp pins = 5.0 v). 20138b-22 output measured parameter value input 2.4 0.8 2.8 0.5 2.4 0.8 2.8 0.5 figure 16. 5.0 v pcmcia ac test reference waveform 3.3 v pcmcia ac test reference waveform this waveform indicates the ac testing method em- ployed for all signals that are pcmcia bus signals when the pcmcia power supply pins are set to 3.3 v (i.e., vddp pins = 3.3 v). 20138b-23 output measured parameter value input 2.0 0.8 2.4 0.4 2.0 0.8 2.4 0.4 figure 17. 3.3 v pcmcia ac test reference waveform p r e l i m i n a r y amd 157 AM79C930 5.0 v non-pcmcia ac test reference waveform this waveform indicates the ac testing method em- ployed for all signals that are not pcmcia bus signals when the appropriate power supply pins are set to 5.0 v (i.e., vddt, vddu1, vddu2, vddm pins = 5.0 v). this includes isa signals, tai interface signals, mem- ory bus interface signals, ieee 1149.1 signals and any other signal not considered to be part of the pcmcia bus interface. 20138b-24 output measured parameter value input 2.0 0.8 2.4 0.45 2.0 0.8 2.4 0.45 figure 18. 5.0 v non-pcmcia ac test reference waveform 3.3 v non-pcmcia ac test reference waveform this waveform indicates the ac testing method em- ployed for all signals that are not pcmcia bus signals when the appropriate power supply pins are set to 3.3 v (i.e., vddt, vddu1, vddu2, vddm pins = 3.3 v). this includes isa signals, tai interface signals, memory bus interface signals, ieee 1149.1 signals and any other signal not considered to be part of the pcmcia bus interface. 20138b-25 output measured parameter value input 2.0 0.8 2.4 0.45 2.0 0.8 2.4 0.45 figure 19. 3.3 v non-pcmcia ac test reference waveform amd p r e l i m i n a r y 158 AM79C930 physical dimensions pqt144 144-pin thin quad flat pack (measured in millimeters) 1.00 ref. 1.60 max 11 ?13 11 ?13 0.50 bsc 144 1 1.35 1.45 21.80 22.20 19.80 20.20 21.80 22.20 19.80 20.20 0.17 0.27 16-038-pqt-2_ah pqt144 5-4-95 ae *for reference only. bsc is an ansi standard for basic space centering. trademarks copyright ? 1997 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. pcnet is a trademark of amd. product names used in this publication are for identification purposes only and may be trademarks of their respective companies. a-1 AM79C930 typical AM79C930 system application appendix a host computer 128k flash 128k sram AM79C930 radio or ir transceiver pcmcia or isa pnp interface 20183a-1 figure 1: typical AM79C930 system application the typical AM79C930 application contains a AM79C930 device, a flash memory device (up to 128 kbytes), an sram memory device (up to 128 kbytes), a network transceiver unit, and a host computer system connected to the AM79C930 subsystem through either the pcmcia or isa plug and play system bus. the flash memory device is used to store pcmcia cis or isa plug and play resource data, the network id for the subsystem and the ieee 802.11 (draft), and the xircom netwave mac protocol firmware that will be executed on the AM79C930 device's embedded 80188 core. the sram will be used by both the device driver and the AM79C930 80188 core for command and status passing, data buffer storage, and 80188 core variable space. in addition to these hardware components, the AM79C930 subsystem will require network application software, a device driver, ieee 802.11 (draft) mac pro- tocol firmware stored in the flash device before power up, and system configuration information (either pcmcia cis or isa plug and play resource data) that is also stored in the flash device before power up. note: the AM79C930 device allows an uninitialized flash memory device to be built into the AM79C930 subsystem and then to be programmed within the AM79C930 subsystem. however, normal configuration utilities present in the system must be disabled before attempting this procedure. the general function of the AM79C930 device is to pro- vide the mac layer functions for an ieee 802.11 (draft) or xircom netwave protocol network. the following sec- tions give a description of the interaction of the AM79C930 device with a device driver, the AM79C930 80188 core firmware, and the network. device configuration the pcmcia pin is strapped in hardware to select either pcmcia or isa plug and play mode of operation. in either case, the host computer at system configuration time (typically at system boot time) will read the configu- ration information from the AM79C930 subsystem flash memory to determine the memory, i/o space, and inter- rupt channel requirements of the subsystem. after allocating a portion of system resources to the AM79C930 subsystem, the device driver will be loaded. the device driver will set up or reserve various areas of the sram for the following purposes: amd a-2 AM79C930 1. command and status communication 2. data buffer areas 3. AM79C930 80188 core variable space after performing these functions, the device driver will enable the 80188 core by writing to a register to release the reset of the AM79C930 80188 core. the AM79C930 80188 core will then begin fetching instruc- tions from the flash memory and will eventually execute code that causes it to recognize the command area that the driver has set up in the sram. the AM79C930 80188 core will begin by initializing reg- isters contained within the tai unit. once this has been completed, status will be written to the sram command and status area, and an interrupt will be sent first to the system interface's status register and then to the system interface bus. the device driver will acknowledge and clear the interrupt, and then will write the next command to the sram command and status area, setting an inter- rupt for the AM79C930 80188 core. flash memory information for system configuration (pcmcia cis or isa plug and play resource data) will normally be pre-programmed in the flash memory along with network id; however, this information may be written to the flash memory the first time through the system interface, before the reset of the AM79C930 80188 core is released. note: normal system configuration utilities must be dis- abled before this is attempted. frame transmission frame transmission is initiated by the device driver. the device driver first places the frame data into the sram in the transmit data buffer area. then the device driver writes the appropriate set of transmit commands to the command area of the sram and sets an interrupt bit in one of the system interface registers. an interrupt to the AM79C930 80188 core will be generated, and the AM79C930 80188 core will respond by examining the command area of the sram. the transmit command will instruct the AM79C930 80188 core to move the transmit data from the data buffer area of sram into the tai unit's transmit (tx) fifo. the move may be accom- plished either through the use of programmed i/o moves or dma moves. dma channel 1 of the 80188 core is reserved for use by the tx fifo. after waiting for appropriate timing intervals as specified in the ieee 802.11 (draft) and the xircom netwave stan- dards, the AM79C930 80188 core will write the transmit command to the tai, and the tai will begin sending the transmit data stream to the transceiver. during the transmission procedure, the tx fifo will require occa- sional refilling. the request for additional tx data will be acknowledged by the AM79C930 80188 core until the entire tx frame has been sent to the transceiver. when the last byte of data has been sent, a cyclic redundancy check (crc) field will automatically be appended to the frame by the tai unit when the crc function has been enabled. preamble and start of frame delimiters will not be automatically generated by the tai unit and, therefore, must be supplied by the firm- ware as part of the data that is loaded into the tx fifo. crc bytes are automatically appended by the tai after the tx fifo empties. when all bytes, including crc bytes, have been sent to the transceiver, tx status information will be gathered and placed in the sram for delivery to the device driver. then, an interrupt to the system will be generated. frame reception frame reception is initiated by the network. when the appropriate network signaling is recognized (a pream- ble plus start of frame delimiter) in the tai unit, the tai will begin placing received data into the receive (rx) fifo. as the rx fifo becomes filled with data, it will re- quest that data be removed by asserting the dma chan- nel 0 input of the AM79C930 80188 core. the 80188 core will move the received data from the rx fifo into the sram data buffer space and will examine the desti- nation address. if the address does not match the ad- dress of the AM79C930 subsystem, then the frame will be rejected by the AM79C930 device. if the frame ad- dress does match the address of the AM79C930 subsystem, then the frame will be accepted. when all bytes of the receive frame have been placed into the sram's data buffer space and the receive status has been placed into the sram, the AM79C930 80188 core will send an interrupt to the system. the device driver will respond to the interrupt by reading the command and status area of the sram. then the device driver will move the received frame from the sram into the sys- tem memory. finally, the device driver will write status to the sram to release the data buffer back to the AM79C930 80188 core for use in a later reception. trademarks copyright ?1998 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. am186, am386, am486, am29000, b imr, eimr, eimr+, gigaphy, himib, ilacc, imr, imr+, imr2, isa-hub, mace, magic packet, pcnet, pcnet- fast , pcnet- fast +, pcnet-mobile, qfex, qfexr, quasi , quest, quiet, taxichip, tpex, and tpex plus are trademarks of advanced micro devices, inc. microsoft is a registered trademark of microsoft corporation. product names used in this publication are for identi?ation purposes only and may be trademarks of their respective companies. |
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